Patents by Inventor Wu-Tsung Hsihe

Wu-Tsung Hsihe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ESD protection for high-voltage-tolerance open-drain output pad
    Patent number: 8493700
    Abstract: A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: July 23, 2013
    Assignee: Elan Microelectronics Corporation
    Inventors: Wu-Tsung Hsihe, Ming-Chun Chou, Ming-Dou Ker
  • ESD protection for high-voltage-tolerance open-drain output pad
    Patent number: 8164870
    Abstract: A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: April 24, 2012
    Assignee: Elan Microelectronics Corporation
    Inventors: Wu-Tsung Hsihe, Ming-Chun Chou, Ming-Dou Ker
  • ESD PROTECTION FOR HIGH-VOLTAGE-TOLERANCE OPEN-DRAIN OUTPUT PAD
    Publication number: 20120044605
    Abstract: A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor.
    Type: Application
    Filed: November 1, 2011
    Publication date: February 23, 2012
    Applicant: ELAN MICROELECTRONICS CORPORATION
    Inventors: WU-TSUNG HSIHE, MING-CHUN CHOU, MING-DOU KER
  • ESD protection for high-voltage-tolerance open-drain output pad
    Publication number: 20090213508
    Abstract: A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor.
    Type: Application
    Filed: January 22, 2009
    Publication date: August 27, 2009
    Inventors: Wu-Tsung Hsihe, Ming-Chun Chou, Ming-Dou Ker