Patents by Inventor Wu Xiang
Wu Xiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12260256Abstract: The application provides a solution for resource scheduling. A method comprises: monitoring the status of online nodes in an online node cluster; in response to the status of the online nodes meeting a hybrid-deployment triggering condition, determining a lending node from the online node cluster; sending a first instruction to the online transaction controller to indicate the online transaction controller to schedule a current online transaction on the lending node to other online node than the lending node in the online node cluster for processing; and in response to the current online transaction on the lending node being scheduled to the other online node, changing a first status tag value of the lending node to a second status tag value, the second status tag value indicating that the lending node is to be scheduled by an offline transaction controller to process offline transactions.Type: GrantFiled: April 16, 2024Date of Patent: March 25, 2025Assignee: DOUYIN VISION CO., LTD.Inventors: Mingmeng Luo, Wei Shao, Yunyao Zhang, Zidong Zhao, Mengyu Zhang, Shuguang Wang, Zongqiang Zhang, Wu Xiang
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Patent number: 12213303Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.Type: GrantFiled: April 21, 2022Date of Patent: January 28, 2025Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yukihiro Nagai, Lu-Yung Lin, Chia-Wei Wu, Tsun-Min Cheng, Yu Chun Lin, Zheng Guo Zhang, Sun-Hung Chen, Wu Xiang Li, Hsiao-Han Lin
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Publication number: 20240264875Abstract: The application provides a solution for resource scheduling. A method comprises: monitoring the status of online nodes in an online node cluster; in response to the status of the online nodes meeting a hybrid-deployment triggering condition, determining a lending node from the online node cluster; sending a first instruction to the online transaction controller to indicate the online transaction controller to schedule a current online transaction on the lending node to other online node than the lending node in the online node cluster for processing; and in response to the current online transaction on the lending node being scheduled to the other online node, changing a first status tag value of the lending node to a second status tag value, the second status tag value indicating that the lending node is to be scheduled by an offline transaction controller to process offline transactions.Type: ApplicationFiled: April 16, 2024Publication date: August 8, 2024Inventors: Mingmeng LUO, Wei SHAO, Yunyao ZHANG, Zidong ZHAO, Mengyu ZHANG, Shuguang WANG, Zongqiang ZHANG, Wu XIANG
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Publication number: 20230284436Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.Type: ApplicationFiled: April 21, 2022Publication date: September 7, 2023Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yukihiro Nagai, Lu-Yung Lin, Chia-Wei Wu, Tsun-Min Cheng, Yu Chun Lin, Zheng Guo Zhang, Sun-Hung Chen, Wu Xiang Li, Hsiao-Han Lin
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Publication number: 20230136711Abstract: The present application discloses a fin structure and a heat exchanger, wherein the fin structure includes: a fin base, the fin base having a tube hole for a heat exchange tube passing through, and the fin base being a corrugated fin; and a plurality of convex parts, the convex part being disposed on the fin base, and the plurality of convex parts surrounding an outer circumference of the tube hole. The fin structure and heat exchanger according to the present application can effectively improve a heat exchange effect of the fin and enhance a heat exchange performance of the heat exchanger.Type: ApplicationFiled: March 5, 2021Publication date: May 4, 2023Inventors: Wu Xiang, Quyang Ma, Ge Yu, Kai Xia, Weixue Lin, Shiqiang Zhang
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Publication number: 20140346791Abstract: The purpose of the present invention is to provide an Animal Pet Waste Collector and a Waste Storage Container. The Animal Pet Waste Collector includes an Operation Stick and a Waste-collecting Bag connected at the front of said Operation Stick. Said Waste-collecting Bag comprises of a Bag and a Ring Frame, with a protruding Fork Lever on the Ring Frame that can be inserted in the Operation Stick's Front End's Socket and clamped. When the User presses a Button on the Operation Stick's Rear End with their fingers, the Fork Lever would detach from the Operation Stick's Socket and cause the Waste-collecting Bag into the trashcan, accomplishing the purpose of collecting animal pet waste in an easy way and fulfilling the environmental needs of keeping the ground waste-free.Type: ApplicationFiled: May 27, 2013Publication date: November 27, 2014Inventors: Yu-Lin Lo, Chia-Chun Lo, Chia-Jing Lo, Wu-Xiang Liu, Dong-Ying Jeng
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Patent number: 8882164Abstract: The purpose of the present invention is to provide an Animal Pet Waste Collector and a Waste Storage Container. The Animal Pet Waste Collector includes an Operation Stick and a Waste-collecting Bag connected at the front of said Operation Stick. Said Waste-collecting Bag comprises of a Bag and a Ring Frame, with a protruding Fork Lever on the Ring Frame that can be inserted in the Operation Stick's Front End's Socket and clamped. When the User presses a Button on the Operation Stick's Rear End with their fingers, the Fork Lever would detach from the Operation Stick's Socket and cause the Waste-collecting Bag into the trashcan, accomplishing the purpose of collecting animal pet waste in an easy way and fulfilling the environmental needs of keeping the ground waste-free.Type: GrantFiled: May 27, 2013Date of Patent: November 11, 2014Inventors: Yu-Lin Lo, Chia-Chun Lo, Chia-Jing Lo, Wu-Xiang Liu, Dong-Ying Jeng
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Patent number: 8089153Abstract: Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug.Type: GrantFiled: December 14, 2009Date of Patent: January 3, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Wu Xiang Hui, Ching-Tien Ma, Man Hua Shen, Chi Yu Shan