Abstract: A compound of formula I wherein X, R1, R2a, R3a, R3b, R4a, R4b, R4c and R5 are defined herein.

Abstract: Compounds of formula Ia and Ib wherein A, B, C and R1 are described herein.

Abstract: A method for fabricating a non-volatile memory of the invention includes providing a substrate, and a tunnel layer is formed on the substrate. A charge-trapping layer is formed on the tunnel layer using silane (SiH4), nitrous oxide (N2O), and ammonia (NH3) as a reactant gas. The charge-trapping layer has a refractive index greater than or equal to 1.49 but less than 1.96 at a wavelength of 633 nm. A top layer is formed on the charge-trapping layer. A gate is formed on the top layer.

Abstract: An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a semiconductor oxide by the oxidant, and the oxide remover subtracts the semiconductor oxide.

Abstract: The present invention provides a gel-casting module, a main electrophoresis assembly, a casting stand for the main electrophoresis assembly and an electrophoresis tank.

Abstract: The method for fabricating the dielectric layer of the present invention is described as follows. A substrate is provided in a chamber, wherein the chamber is a single-wafer LPCVD chamber. A silicon source gas, an oxidation source gas and a nitridation source gas are then introduced into the chamber, wherein a volumetric flow rate ratio of the oxidation source gas to a total amount of the oxidation source gas and the nitridation source gas is varied within a range of 0.0245 to 0.375. Afterwards, the dielectric layer with a dielectric constant within a range of 4.8 to 7.6 is formed on the substrate.

Abstract: A compound of formula I wherein A, X, q, R1, R2a, R2b, R2c, R3a, and R3b are defined herein.

Abstract: A method of improving the intrinsic gettering ability of a wafer is described. A first annealing step is performed to the wafer at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. A second annealing step is performed to the wafer, at a second temperature higher than the first temperature, in the atmosphere.

Abstract: The present invention discloses a sub-rate transmission method for user data services in transmission devices of a Metropolitan Area Network (MAN). The method comprises the steps of: pre-configuring each transmission device to form forwarding table items representing corresponding relationship between self-defined tags and transmission lines; after receiving a user data frame, an original transmission device nesting a self-defined tag into the user data frame according to the forwarding table items to form a self-defined data frame, then transmitting the self-defined data frame; and after receiving the self-defined data frame, a terminal transmission device determining an output port for transferring the data frame by searching the forwarding table items with the nested self-defined tag, then deleting the nested self-defined tag and sending the original user data frame to the output port.

Abstract: Compounds of formula Ia and Ib wherein A, B, C and R1 are described herein.

Abstract: Provided herein are multi-stage broadband amplifier configured to achieve a high gain-bandwidth product in a non-distributed architecture and methods for designing the same. The broadband amplifier can include an input stage having a broadband matching unit and an input buffer unit, a gain stage having an RLC network and a amplifier unit and an output stage having a common collector amplifier and an RC compensation unit.

Abstract: Solar-powered device having a body for housing at least one energy storage module and at least one control module are disclosed. The body includes an opening formed by at least two recesses disposed about an upper surface of the body. At least one solar panel may be coupled to the upper surface of the body where the solar panel may be received by the recesses.

Abstract: An interconnection process is provided. The process includes the following steps. Firstly, a semiconductor base having at least a electrical conductive region is provided. Next, a dielectric layer with a contact hole is formed to cover the semiconductor base, wherein the contact hole exposes part of the electrical conductive region. Then, a thermal process is performed on the semiconductor base covered with the dielectric layer. Lastly, a conductive layer is formed on the dielectric layer, wherein the conductive layer is electrically connected to the electrical conductive region through the contact hole.

Abstract: A flow control method of MAN transmission equipment is disclosed wherein when congestion occurs in a data transmission port of a data transmission equipment at a receiving end, an Ethernet flow control frame is fed back to a transmission equipment at a sending end, to perform flow control of the data transmission port. When congestion occurs in a board of the data transmission port, a board-level flow control frame is fed back to a packet forwarding module of the data transmission port, to perform flow control of the board. When congestion occurs in a logical sub-channel of the board, a channel-level flow control frame is fed back to the packet forwarding module of the data transmission port, to perform flow control of the logical sub-channel. The disclosed method comprises implementation of flow control strategy of MAN transmission equipment, making MAN flow control strategy more preferable, and satisfying flow control service requirement of a complicated Ethernet MAN transmission equipment.

Abstract: A system includes a mounting device (200), a detecting device (100), and a circuit (300). The mounting device includes a base (210), and a mounting head (220) opposite to the base. The detecting device is fixed on the base, and includes a shell (110) comprising a cavity (112) therein, a probe (130) fixed in the cavity and protruding towards the through hole, and a plug (150) having a pin (152) made of conductive materials. The shell further includes an opening (118) communicating with the cavity, and a through hole (114) formed opposite to the mounting head and communicating with the cavity. The pin is connected to the probe through the opening. The circuit includes a PLC circuit (320), and a power supply (310) connected with the PLC circuit. The pin connects with one of the PLC circuit and power circuit, and the mounting head connects with the remaining one.

Abstract: A method of forming word lines of a memory includes providing a substrate and forming a conductive layer on the substrate. A metal silicide layer is formed on the conductive layer, and a mask pattern is formed on the metal silicide layer. A mask liner covering the mask pattern and the surface of the metal silicide layer is formed on the substrate to shorten distances between the word line regions. An etching process is performed on the mask liner and the mask pattern until the partial surface of the metal silicide layer is exposed. The metal silicide layer and the conductive layer are etched to form word lines by utilizing the mask liner and the mask pattern as a mask. A silicon content of the metal silicide layer must be less than or equal to 2 for reducing a bridge failure rate between the word lines.

Abstract: A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer.

Abstract: A method of forming word lines of a memory includes providing a substrate and forming a conductive layer on the substrate. A metal silicide layer is formed on the conductive layer, and a mask pattern is formed on the metal silicide layer. A mask liner covering the mask pattern and the surface of the metal silicide layer is formed on the substrate to shorten distances between the word line regions. An etching process is performed on the mask liner and the mask pattern until the partial surface of the metal silicide layer is exposed. The metal silicide layer and the conductive layer are etched to form word lines by utilizing the mask liner and the mask pattern as a mask. A silicon content of the metal silicide layer must be less than or equal to 2 for reducing a bridge failure rate between the word lines.

Abstract: A method of manufacturing an integrated circuit with a small pitch comprises providing a second material layer patterned to form at least two features with an opening between the features. The second material layer is formed over a first material layer and the first material layer is over a substrate. The method also comprises providing a first oxide layer to form a first sidewall surrounding each of the features, and providing a second oxide layer over the first sidewalls and the first material layer. A second sidewall is formed surrounding each of the features. The method further comprises providing a conductive layer over the second oxide layer and removing the conductive layer, the second sidewalls and the first material underneath the second sidewalls.

Abstract: A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns.