Patents by Inventor Wubing GAN

Wubing GAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Ultra low-power pipelined processor
    Patent number: 8972812
    Abstract: A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 3, 2015
    Assignee: University of Electronic Science and Technology of China
    Inventors: Yajuan He, Tingting Xia, Tao Luo, Wubing Gan, Bo Zhang
  • ULTRA LOW-POWER PIPELINED PROCESSOR
    Publication number: 20140304572
    Abstract: A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage.
    Type: Application
    Filed: June 27, 2013
    Publication date: October 9, 2014
    Inventors: Yajuan HE, Tingting XIA, Tao LUO, Wubing GAN, Bo ZHANG