Patents by Inventor Wun-Jie Lin

Wun-Jie Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250133838
    Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a first resistance-capacitance (RC) timer circuit, a second RC timer circuit, a voltage pull-down circuit, a voltage pull-up circuit, a discharge circuit, and a discharge control circuit. The first RC timer circuit is coupled between a first power supply voltage and a reference voltage. The second RC timer circuit is coupled between a second power supply voltage and the reference voltage. The voltage pull-up circuit is coupled between the second power supply voltage and the reference voltage through a first resistor. The discharge circuit is coupled between the second power supply voltage and the reference voltage. The discharge control circuit is coupled between a third node and the reference voltage, and controls the discharge circuit using a first voltage generated by the first RC timer circuit.
    Type: Application
    Filed: October 19, 2023
    Publication date: April 24, 2025
    Inventors: LI-WEI CHU, WUN-JIE LIN
  • Publication number: 20250132558
    Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit o discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 24, 2025
    Inventors: LI-WEI CHU, WUN-JIE LIN
  • Publication number: 20250125611
    Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Li-Wei Chu, Tao Yi Hung, Chia-Hui Chen, Wun-Jie Lin, Jam-Wem Lee
  • Publication number: 20250107244
    Abstract: A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.
    Type: Application
    Filed: September 25, 2023
    Publication date: March 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Wei Chu, Jam-Wem Lee, Wun-Jie Lin, Shou Ming Liu
  • Publication number: 20250098328
    Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a doped region in the substrate. The semiconductor device further includes an active area, and wherein the active area comprises an emitter region and a collector region, wherein the emitter region is electrically connected to the doped region. The semiconductor device further includes a deep trench isolation (DTI) structure extending through the active area and between the emitter region and the collector region.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Inventors: Tzu-Hao CHIANG, Wun-Jie LIN, Jam-Wem LEE
  • Publication number: 20250089379
    Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.
    Type: Application
    Filed: November 26, 2024
    Publication date: March 13, 2025
    Inventors: Tao-Yi HUNG, Wun-Jie LIN, Jam-Wem LEE, Kuo-Ji CHEN
  • Publication number: 20250072108
    Abstract: Capacitor cells are provided. A first PMOS transistor has a source connected to a power supply and a drain connected to a first node. A first NMOS transistor has a source connected to a ground and a drain connected to a second node. A second PMOS transistor has a source connected to the second node and a drain connected to the first node. A second NMOS transistor has a source connected to the ground and a drain connected to the first node. A first P+ doped region is shared by drains of the first and second PMOS transistors. A first gate metal is between the first P+ doped region and a second P+ doped region. A first N+ doped region is shared by sources of the first and second NMOS transistors. A second gate metal is between the first N+ doped region and a second N+ doped region.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Inventors: Chien-Yao HUANG, Wun-Jie LIN, Chia-Wei HSU, Yu-Ti SU
  • Publication number: 20250062138
    Abstract: A method for fabricating a package structure is provided. The method includes premixing cellulose nanofibrils (CNFs) and a graphene material in a solvent to form a solution; removing the solvent from the solution to form a composite filler; mixing a prepolymeric material with the composite filler to form a composite material; and performing a molding process using the composite material.
    Type: Application
    Filed: August 18, 2023
    Publication date: February 20, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Tzu-Hsuan CHANG, Rong-Teng Lin, Bi-Xian Wu, Teng-Chin Hsu, Yun-Hong Yang, Chien-Liang Chen, Jam-Wem Lee, Kuo-Ji Chen, Wun-Jie Lin
  • Publication number: 20250038524
    Abstract: Devices, circuits, and methods for electrostatic discharge (ESD) protection are provided. An electrostatic discharge (ESD) protection circuit comprises a first transistor connected between a first voltage and a second voltage, and a first control circuit connected between the first voltage and the second voltage, and configured to supply a control signal to the first transistor. The circuit further comprises a second transistor connected between the second voltage and a third voltage, and a second control circuit connected between the second voltage and the third voltage, and configured to supply a control signal to the second transistor. The first control circuit and the second control circuit are connected to each other via a first interconnect and a second interconnect. The first and second transistors are configured to turn on in response to an ESD event.
    Type: Application
    Filed: July 26, 2023
    Publication date: January 30, 2025
    Inventors: Jam-Wem Lee, Wun-Jie Lin, Chia-Jung Chang, Li-Wei Chu
  • Patent number: 12191655
    Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.
    Type: Grant
    Filed: November 20, 2023
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Wei Chu, Tao Yi Hung, Chia-Hui Chen, Wun-Jie Lin, Jam-Wem Lee
  • Patent number: 12176341
    Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.
    Type: Grant
    Filed: November 18, 2023
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao-Yi Hung, Wun-Jie Lin, Jam-Wem Lee, Kuo-Ji Chen
  • Patent number: 12170283
    Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: December 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Yao Huang, Wun-Jie Lin, Chia-Wei Hsu, Yu-Ti Su
  • Patent number: 12166030
    Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a doped well in the substrate, wherein the doped well comprises a first concentration of dopants of a first type in the substrate. The semiconductor device further includes a doped region in the substrate, wherein the doped region comprises a second concentration of the dopants of the first type, the doped region extends around the doped well, and the doped region is electrically insulated from the doped well. The semiconductor device further includes an active area, and wherein the active area comprises an emitter region and a collector region, wherein the emitter region is electrically connected to the doped region. The semiconductor device further includes a deep trench isolation (DTI) structure extending through the active area and between the emitter region and the collector region.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Hao Chiang, Wun-Jie Lin, Jam-Wem Lee
  • Publication number: 20240405012
    Abstract: An electrostatic discharge (ESD) protection cell region (of a semiconductor device) includes a resistor-diode ladder and a power clamp circuit coupled in parallel between a first power rail PR1 and a second power rail PR2. The resistor-diode ladder is also coupled between an input/output (I/O) pad of the semiconductor device and core circuitry of the semiconductor device. The resistor-diode ladder includes: a first diode coupled between a first node and the first power rail; a first resistor coupled between the first node and a second node; a second diode coupled between the second node and the first power rail; a third diode coupled between the first node and the second power rail; and a fourth diode coupled between the second node and the second power rail. The first node is coupled to the I/O pad. The resistor-diode ladder is coupled between the I/O pad and the core circuitry.
    Type: Application
    Filed: November 9, 2023
    Publication date: December 5, 2024
    Inventors: Li-Wei ChU, Jam-Wem LEE, Wun-Jie LIN, Shou Ming LIU
  • Publication number: 20240395799
    Abstract: A method of manufacturing a snapback electrostatic discharge (ESD) protection circuit includes fabricating a first well in a substrate, the first well extending in a first direction, and having a first dopant type, fabricating a drain region of a transistor in the first well, the drain region having a second dopant type, fabricating a source region of the transistor in the first well, the source region extending in the first direction, having the second dopant type, and being separated from the drain region in a second direction, fabricating a second well in the first well, the second well extending in the first direction, having the second dopant type, and being adjacent to a portion of the drain region, and fabricating a gate region of the transistor, the gate region being between the drain region and the source region, and being over the first well and the substrate.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Chia-Lin HSU, Yu-Hung YEH, Yu-Ti SU, Wun-Jie LIN
  • Publication number: 20240387554
    Abstract: A method of manufacturing an integrated circuit (IC) device includes forming, over a substrate, at least one first well region of a first semiconductor type, and a second well region of a second semiconductor type different from the first semiconductor type. The method further includes forming a plurality of first doped regions of the first semiconductor type over the at least one first well region, and a second doped region of the second semiconductor type over the second well region. Each of the plurality of first doped regions has a first length in a first direction. The second doped region extends in the first direction between at least two first doped regions among the plurality of first doped regions over a second length greater than the first length.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 21, 2024
    Inventors: Chien Yao HUANG, Wun-Jie LIN, Kuo-Ji CHEN
  • Publication number: 20240386180
    Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
  • Publication number: 20240387507
    Abstract: A method of making a semiconductor device includes manufacturing lines extending in a first direction over doped zones in a substrate, wherein each of the lines has a line width measured along a first direction. The method further includes trimming the lines into line segments having ends over an isolation structure. The method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the first direction, and the line width is substantially similar to the gate electrode width.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Li-Wei CHU, Wun-Jie LIN, Yu-Ti SU, Ming-Fu TSAI, Jam-Wem LEE
  • Publication number: 20240363621
    Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: Yu-Hung YEH, Wun-Jie LIN, Jam-Wem LEE
  • Publication number: 20240347483
    Abstract: A semiconductor device includes a device wafer including a first side and a second side opposite to each other, and a carrier wafer disposed over the first side of the device wafer. The carrier wafer includes an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a first diode and a second diode. The first diode is operatively coupled to a first power rail, and the second diode is operatively coupled to a second power rail at least through the device wafer.
    Type: Application
    Filed: June 21, 2024
    Publication date: October 17, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tao-Yi Hung, Jam-Wem Lee, Kuo-Ji Chen, Wun-Jie Lin