Patents by Inventor Wun-Jie Lin

Wun-Jie Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220139903
    Abstract: A method for fabricating an integrated circuit is provided. The method includes etching a first recess in a semiconductor structure; forming a first doped epitaxial feature in the first recess; and forming a second doped epitaxial feature over the first doped epitaxial feature, wherein the second doped epitaxial feature has a conductive type opposite to a conductive type of the first doped epitaxial feature.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tao-Yi HUNG, Wun-Jie LIN, Jam-Wem LEE, Kuo-Ji CHEN, Chia-En HUANG
  • Publication number: 20220037365
    Abstract: An integrated circuit (IC) device includes a plurality of TAP cells arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of TAP cells includes at least one first TAP cell. The first TAP cell includes two first end areas and a first middle area arranged consecutively in the second direction. The first middle area includes a first dopant of a first type implanted in a first well region of the first type. The first end areas are arranged on opposite sides of the first middle area in the second direction. Each of the first end areas includes a second dopant of a second type implanted in the first well region, the second type different from the first type.
    Type: Application
    Filed: July 28, 2020
    Publication date: February 3, 2022
    Inventors: Chien Yao HUANG, Wun-Jie LIN, Kuo-Ji CHEN
  • Publication number: 20210366846
    Abstract: A semiconductor device includes a device wafer having a first side and a second side. The first and second sides are opposite to each other. The semiconductor device includes a plurality of first interconnect structures disposed on the first side of the device wafer. The semiconductor device includes a plurality of second interconnect structures disposed on the second side of the device wafer. The plurality of interconnect structures comprise a first power rail and a second power rail. The semiconductor device includes a carrier wafer disposed over the plurality of first interconnect structures. The semiconductor device includes an electrostatic discharge (ESD) protection circuit formed over a side of the carrier wafer. The ESD protection circuit is operatively coupled to the first and second power rails.
    Type: Application
    Filed: March 26, 2021
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Tao Yi Hung, Jam-Wem Lee, Kuo-Ji Chen, Wun-Jie Lin
  • Publication number: 20210305802
    Abstract: An electrostatic discharge (ESD) protection circuit includes a first diode, a second diode and an ESD clamp circuit. The first diode is in a semiconductor wafer, and is coupled to an input output (IO) pad. The second diode is in the semiconductor wafer, and is coupled to the first diode and the IO pad. The ESD clamp circuit is in the semiconductor wafer, and is coupled to the first diode and the second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer. The first signal tap region is coupled to a first voltage supply. The first diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit.
    Type: Application
    Filed: January 12, 2021
    Publication date: September 30, 2021
    Inventors: Yu-Hung YEH, Wun-Jie LIN, Jam-Wem LEE
  • Publication number: 20210305235
    Abstract: A snapback electrostatic discharge (ESD) protection circuit includes a first well in a substrate, a drain region of a transistor, a source region of the transistor, a gate region of the transistor, and a second well embedded in the first well. The first well has a first dopant type. The drain region is in the first well, and has a second dopant type different from the first dopant type. The source region is in the first well, has the second dopant type, and is separated from the drain region in a first direction. The gate region is over the first well and the substrate. The second well is embedded in the first well, and is adjacent to a portion of the drain region. The second well has the second dopant type.
    Type: Application
    Filed: January 7, 2021
    Publication date: September 30, 2021
    Inventors: Chia-Lin HSU, Yu-Hung YEH, Yu-Ti SU, Wun-Jie LIN
  • Publication number: 20210305809
    Abstract: A clamp circuit includes an electrostatic discharge (ESD) detection circuit coupled between a first node and a second node. The clamp circuit further includes a first transistor of a first type. The first transistor has a first gate coupled to at least the ESD detection circuit by a third node, a first drain coupled to the first node and a first source coupled to the second node. The clamp circuit further includes a charging circuit coupled between the second node and the third node, and configured to charge the third node during an ESD event at the second node.
    Type: Application
    Filed: December 1, 2020
    Publication date: September 30, 2021
    Inventors: Tao Yi HUNG, Ming-Fang LAI, Li-Wei CHU, Wun-Jie LIN, Jam-Wem LEE
  • Publication number: 20210272984
    Abstract: An integrated circuit (IC) device includes a plurality of first TAP cells of a first semiconductor type, and a plurality of second TAP cells of a second semiconductor type different from the first semiconductor type. The plurality of first TAP cells is arranged in at least two columns, the at least two columns adjacent each other in a first direction and extending in a second direction transverse to the first direction. Each of the plurality of first TAP cells has a first length in the first direction. The plurality of second TAP cells includes at least one second TAP cell extending in the first direction between the at least two columns over a second length greater than the first length of each of the plurality of first TAP cells in the first direction.
    Type: Application
    Filed: September 17, 2020
    Publication date: September 2, 2021
    Inventors: Chien Yao HUANG, Wun-Jie LIN, Kuo-Ji CHEN
  • Publication number: 20210210490
    Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate connected to the second node. A second NMOS transistor is coupled between the first node and the ground, a gate connected to the first node, and has a gate connected to the first node. Sources of the first and second PMOS transistors share a P+ doped region in N-type well region, and the first PMOS transistor is disposed between the second PMOS transistor and the first and second NMOS transistors.
    Type: Application
    Filed: March 24, 2021
    Publication date: July 8, 2021
    Inventors: Chien-Yao Huang, Wun-Jie Lin, Chia-Wei Hsu, Yu-Ti Su
  • Publication number: 20210117605
    Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 22, 2021
    Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Mohammed Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
  • Patent number: 10971495
    Abstract: A capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the first node, and has a gate connected to the second node. A second NMOS transistor has a drain connected to the first node, a gate connected to the first node, and a source connected to the ground or the second node. The first and second PMOS transistors and the first and second NMOS transistors are arranged in the same row. The second PMOS transistor is disposed between the first PMOS transistor and the first and second NMOS transistors.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chien-Yao Huang, Wun-Jie Lin, Chia-Wei Hsu, Yu-Ti Su
  • Publication number: 20210091176
    Abstract: A method includes implanting a first guard ring around a periphery of core circuitry. The implanting of the first guard ring includes implanting a first component a first distance from the core circuitry on a first side of the core circuitry, and implanting a second component a second distance from the core circuitry on a second side of the core circuitry, wherein the second distance is greater than the first distance. The method further includes implanting a second guard ring around the periphery of the core circuitry. The implanting of the second guard ring includes implanting a third component a third distance from the core circuitry on the first side of the core circuitry, and implanting a fourth component a fourth distance from the core circuitry on the second side of the core circuitry, wherein the third distance is greater than the fourth distance.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 25, 2021
    Inventors: Wan-Yen LIN, Wun-Jie LIN, Yu-Ti SU, Bo-Ting CHEN, Jen-Chou TSENG, Kuo-Ji CHEN, Sun-Jay CHANG, Min-Chang LIANG
  • Publication number: 20210082907
    Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: Wun-Jie Lin, Han-Jen Yang, Yu-Ti Su
  • Patent number: 10872190
    Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 22, 2020
    Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
  • Patent number: 10868112
    Abstract: A circuit device includes core circuitry. The circuit device further includes a guard ring surrounding the core circuitry. The guard ring includes a first plurality of fin structures arranged in a first direction parallel to a first side of the core circuitry, wherein adjacent fin structures of the first plurality of fin structures are separated by a first distance. The guard ring further includes a second plurality of fin structures arranged in a second direction parallel to a second side of the core circuitry, wherein adjacent fin structures of the second plurality of fin structures are separated by a second distance, and the second distance is smaller than the first distance.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yen Lin, Wun-Jie Lin, Yu-Ti Su, Bo-Ting Chen, Jen-Chou Tseng, Kuo-Ji Chen, Sun-Jay Chang, Min-Chang Liang
  • Patent number: 10854595
    Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wun-Jie Lin, Han-Jen Yang, Yu-Ti Su
  • Publication number: 20200373294
    Abstract: Systems and methods for protecting a device from an electrostatic discharge (ESD) event are provided. A resistor-capacitor (RC) trigger circuit and a driver circuit are provided. The RC trigger circuit is configured to provide an ESD protection signal to the driver circuit. A discharge circuit includes a first metal oxide semiconductor (MOS) transistor and a second MOS transistor connected in series between a first voltage potential and a second voltage potential. The driver circuit provides one or more signals for turning the first and second MOS transistors on and off.
    Type: Application
    Filed: August 14, 2020
    Publication date: November 26, 2020
    Inventors: Shu-Yu Su, Jam-Wem Lee, Wun-Jie Lin
  • Patent number: 10790274
    Abstract: An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ti Su, Wun-Jie Lin, Han-Jen Yang, Shui-Ming Cheng, Ming-Hsiang Song
  • Patent number: 10777547
    Abstract: Systems and methods for protecting a device from an electrostatic discharge (ESD) event are provided. A resistor-capacitor (RC) trigger circuit and a driver circuit are provided. The RC trigger circuit is configured to provide an ESD protection signal to the driver circuit. A discharge circuit includes a first metal oxide semiconductor (MOS) transistor and a second MOS transistor connected in series between a first voltage potential and a second voltage potential. The driver circuit provides one or more signals for turning the first and second MOS transistors on and off.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shu-Yu Su, Jam-Wem Lee, Wun-Jie Lin
  • Publication number: 20200035681
    Abstract: A capacitor cell is provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the first node, and has a gate connected to the second node. A second NMOS transistor has a drain connected to the first node, a gate connected to the first node, and a source connected to the ground or the second node. The first and second PMOS transistors and the first and second NMOS transistors are arranged in the same row. The second PMOS transistor is disposed between the first PMOS transistor and the first and second NMOS transistors.
    Type: Application
    Filed: October 2, 2019
    Publication date: January 30, 2020
    Inventors: Chien-Yao HUANG, Wun-Jie LIN, Chia-Wei HSU, Yu-Ti SU
  • Patent number: 10546850
    Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: January 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wun-Jie Lin, Ching-Hsiung Lo, Jen-Chou Tseng, Han-Jen Yang, Arabinda Das