Abstract: A power electronics system, comprising a first inverter configured to receive DC power from a power source and a second inverter configured to receive DC power from the power source is provided. The system includes a first output inductor connected in series to an output of the first inverter, a second output inductor connected in series to an output of the second inverter, a coupling inductor configured to receive current from the first output inductor and the second output inductor, and an AC power output.

Abstract: A power electronics system, comprising a first inverter configured to receive DC power from a power source and a second inverter configured to receive DC power from the power source is provided. The system includes a first output inductor connected in series to an output of the first inverter, a second output inductor connected in series to an output of the second inverter, a coupling inductor configured to receive current from the first output inductor and the second output inductor, and an AC power output.

Abstract: A power electronics system, comprising a first inverter configured to receive DC power from a power source and a second inverter configured to receive DC power from the power source is provided. The system includes a first output inductor connected in series to an output of the first inverter, a second output inductor connected in series to an output of the second inverter, a coupling inductor configured to receive current from the first output inductor and the second output inductor, and an AC power output.

Abstract: A power electronics system, comprising a first inverter configured to receive DC power from a power source and a second inverter configured to receive DC power from the power source is provided. The system includes a first output inductor connected in series to an output of the first inverter, a second output inductor connected in series to an output of the second inverter, a coupling inductor configured to receive current from the first output inductor and the second output inductor, and an AC power output.

Abstract: A power adaptor system including a system side and a power adaptor side is provided. The system side includes a first connector, a system circuit, a storage capacitor, and a first microcontroller. The storage capacitor is charged by an initial voltage received via the first connector. The first microcontroller outputs a system side setting after the storage capacitor is completely charged. The power adaptor side includes a second connector, a power adaptor circuit, and a second microcontroller. The second connector is for electrically connecting to the first connector. The second microcontroller receives the system side setting via the second connector, and controls the power adaptor circuit to output an operating voltage required by the system circuit according to the system side setting.

Abstract: A 3D stereo display method and a device thereof. Two sets of shutters are disposed in a display. The shutters are complementarily interlaced with each other. The opening/closing of the two sets of shutters are controlled by time interval concept. When the display frequency is odd frequency, one set of shutters is activated. When the display frequency is even frequency, the other set of shutters is activated. The two sets of shutters are continuously opened and closed according to the variation of the frequency so that in odd and even frequencies, the left and right eyes can respectively see independent images formed of different subpixels. Therefore, a 3D display effect is presented to bare eyes without reducing resolution.

Abstract: This invention relates to a method for yield loss analysis of process steps of semiconductor wafers having a plurality of dies, and more particularly relates to a defect inspection technique to determine a hit ratio, computation of yield impact contributions for the defects, and determination of a kill ratio for a specific type of defect. Yield loss is estimated ultimately upon a choice of a defect density distribution function. A defect calibrated factor and a yield impact calibrated factor are introduced herein.

Abstract: This invention relates to a method for yield loss analysis of process steps of semiconductor wafers having a plurality of dies, and more particularly relates to a defect inspection technique to determine a hit ratio, computation of yield impact contributions for the defects, and determination of a kill ratio for a specific type of defect. Yield loss is estimated ultimately upon a choice of a defect density distribution function. A defect calibrated factor and a yield impact calibrated factor are introduced herein.