Patents by Inventor Wuping Liu
Wuping Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9449834Abstract: A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide layers are formed on sidewalls and bottom of the recess by oxygen ion implantation process, wherein oxide layer on sidewalls of recess is thinner than oxide layer on bottom of recess. Thereafter, oxide layer on sidewalls of recess is completely removed, and only a portion of oxide layer on bottom of recess remains. Then, sidewalls of recess are shaped into ? form by orientation selective wet etching using oxide layer remained on bottom of recess as a stop layer. Finally, oxide layer on bottom of recess is removed. By forming oxide layer on bottom of recess and using it as stop layer in subsequent orientation selective wet etching, the disclosed method can prevent a ?-shaped recess with a cuspate bottom.Type: GrantFiled: November 4, 2011Date of Patent: September 20, 2016Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Qingsong Wei, Wei Lu, Wuping Liu, Yonggen He
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Patent number: 9443761Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes providing a semiconductor device with a metal silicide electrically coupled thereto. A contact opening exposing the metal silicide is formed to the semiconductor device. A conductive material is deposite within the contact opening to form a contact to the metal silicide while simultaneously forming a contact seam void within the contact. A self-aligned conductive material is deposited within the contact to form a conductive plug that at least partially fills the contact seam void, and a metallization layer is deposited overlying the contact.Type: GrantFiled: July 29, 2014Date of Patent: September 13, 2016Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wei Shao, Fan Zhang, Wuping Liu, Wei Lu, Vish Srinivasan, Juan Boon Tan
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Publication number: 20160035623Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes providing a semiconductor device with a metal silicide electrically coupled thereto. A contact opening exposing the metal silicide is formed to the semiconductor device. A conductive material is deposited within the contact opening to form a contact to the metal silicide while simultaneously forming a contact seam void within the contact. A self-aligned conductive material is deposited within the contact to form a conductive plug that at least partially fills the contact seam void, and a metallization layer is deposited overlying the contact.Type: ApplicationFiled: July 29, 2014Publication date: February 4, 2016Inventors: Wei Shao, Fan Zhang, Wuping Liu, Wei Lu, Vish Srinivasan, Juan Boon Tan
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Patent number: 8358007Abstract: A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.Type: GrantFiled: June 8, 2010Date of Patent: January 22, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Dong Kyun Sohn, Wuping Liu, Fan Zhang, Juan Boon Tan, Jing Hui Li, Bei Chao Zhang, Luying Du, Wei Liu, Yeow Kheng Lim
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Publication number: 20130017656Abstract: A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide layers are formed on sidewalls and bottom of the recess by oxygen ion implantation process, wherein oxide layer on sidewalls of recess is thinner than oxide layer on bottom of recess. Thereafter, oxide layer on sidewalls of recess is completely removed, and only a portion of oxide layer on bottom of recess remains. Then, sidewalls of recess are shaped into ? form by orientation selective wet etching using oxide layer remained on bottom of recess as a stop layer. Finally, oxide layer on bottom of recess is removed. By forming oxide layer on bottom of recess and using it as stop layer in subsequent orientation selective wet etching, the disclosed method can prevent a ?-shaped recess with a cuspate bottom.Type: ApplicationFiled: November 4, 2011Publication date: January 17, 2013Applicant: Semiconductor Manufacturing International (Beijing) CorporationInventors: Qingsong Wei, Wei Lu, Wuping Liu, Yonggen He
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Patent number: 8018061Abstract: An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening.Type: GrantFiled: September 25, 2009Date of Patent: September 13, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Wuping Liu, Michael Beck, John A. Fitzsimmons
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Patent number: 7906426Abstract: An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.Type: GrantFiled: April 23, 2007Date of Patent: March 15, 2011Assignees: Globalfoundries Singapore Pte. Ltd., International Business Machines Corporation, Infineon Technologies AGInventors: Wuping Liu, Johnny Widodo, Teck Jung Tang, Jing Hui Li, Han Wah Ng, Larry A. Clevenger, Hermann Wendt
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Publication number: 20100314763Abstract: A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.Type: ApplicationFiled: June 8, 2010Publication date: December 16, 2010Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Dong Kyun Sohn, Wuping Liu, Fan Zhang, Juan Boon Tan, Jing Hui Li, Bei Chao Zhang, Luying Du, Wei Liu, Yeow Kheng Lim
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Publication number: 20100109155Abstract: A semiconductor device includes a dielectric layer in which an upper portion is densified. An interconnection is disposed in the dielectric layer. The densified portion reduces undercut during subsequent processing, improving reliability of the interconnection.Type: ApplicationFiled: November 5, 2008Publication date: May 6, 2010Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Huang LIU, Johnny WIDODO, Yihua WANG, Wuping LIU, Ti OUYANG, Wei LU
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Patent number: 7678586Abstract: An example embodiment is a method of curing a film over a semiconductor structure. We provide a semiconductor structure comprised of a substrate and an interconnect structure. We provide a film over the semiconductor structure. We provide an electron source, an anode grid between the electron source and the semiconductor structure. We cure the film by exposing the film to an electron beam from the electron source that passes through the anode grid. We control the electron beam by controlling the bias voltage between the anode grid and the semiconductor structure. Another embodiment is a tool for curing a film.Type: GrantFiled: December 8, 2005Date of Patent: March 16, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Huang Liu, Bei Chao Zhang, Wuping Liu, John Leonard Sudijono, Liang Choo Hsia
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Publication number: 20100013104Abstract: An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening.Type: ApplicationFiled: September 25, 2009Publication date: January 21, 2010Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING LTD., INFINEON TECHNOLOGIES NORTH AMERICA CORP., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wuping Liu, Michael Beck, John A. Fitzsimmons
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Patent number: 7615484Abstract: An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.Type: GrantFiled: April 24, 2007Date of Patent: November 10, 2009Assignees: Chartered Semiconductor Manufacturing Ltd., Infineon Technologies North America Corp., International Business Machines CorporationInventors: Wuping Liu, Michael Beck, John A. Fitzsimmons
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Patent number: 7601607Abstract: An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.Type: GrantFiled: May 15, 2006Date of Patent: October 13, 2009Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Wuping Liu, Raymond Joy, Beichao Zhang, Liang Choo Hsia, Boon Meng Seah, Shyam Pal
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Publication number: 20080265409Abstract: An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.Type: ApplicationFiled: April 24, 2007Publication date: October 30, 2008Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING LTD., INFINEON TECHNOLOGIES NORTH AMERICA CORP., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wuping Liu, Michael Beck, John A. Fitzsimmons
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Publication number: 20080258308Abstract: An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.Type: ApplicationFiled: April 23, 2007Publication date: October 23, 2008Inventors: Wuping Liu, Johnny Widodo, Teck Jung Tang, Jing Hui Li, Han Wah Ng, Larry A. Clevenger, Hermann Wendt
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Publication number: 20080230907Abstract: An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; forming a via opening through the low-K dielectric layer to the interconnect layer; and forming a carbon implant region around the via opening, a trench opening, or a combination thereof, for protecting the low-K dielectric layer.Type: ApplicationFiled: March 22, 2007Publication date: September 25, 2008Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING LTD., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wuping Liu, Kevin S. Petrarca, Johnny Widodo, Lawrence A. Clevenger, Wai-Kin Li
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Patent number: 7372156Abstract: An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer; and a patterned middle dielectric material layer; the lower and middle dielectric layers being comprised of the same material. An upper trench opening in the patterned bottom etch stop layer and the patterned lower dielectric material layer; and a lower via opening in the patterned middle etch stop layer and the patterned middle dielectric material layer. The lower via opening being in communication with the upper trench opening. Wherein the upper trench opening and the lower via opening comprise an aligned dual damascene opening.Type: GrantFiled: July 5, 2005Date of Patent: May 13, 2008Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yeow Kheng Lim, Wuping Liu, Tae Jong Lee, Bei Chao Zhang, Juan Boon Tan, Alan Cuthbertson, Chin Chuan Neo
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Patent number: 7323408Abstract: A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etched, exposing the surface of the pattern of copper interconnects. The exposed copper surface is Ar sputtered after which a first barrier layer is deposited. The patterned and etched layer of protective material is removed, leaving in place overlying the pattern of copper interconnects a protective layer of first barrier material. A dielectric barrier layer, in the form of a layer of etch stop material, is deposited after which additional layers of dielectric interspersed with layers of etch stop material are deposited. Via and trench patterns are etched aligned with a copper pattern to which an electrical contact is to be established, the copper pattern being protected by the first layer of barrier material.Type: GrantFiled: December 12, 2005Date of Patent: January 29, 2008Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Beichao Zhang, Wuping Liu, Liang-Choo Hsia
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Publication number: 20070264820Abstract: An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.Type: ApplicationFiled: May 15, 2006Publication date: November 15, 2007Inventors: Wuping Liu, Raymond Joy, Beichao Zhang, Liang Hsia, Boon Seah, Shyam Pal
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Patent number: 7276440Abstract: In accordance with the objectives of the invention a new design and method for the implementation thereof is provided in the form of an “oxide ring”. A conventional die is provided with a guard ring or sealing ring, which surrounds and isolates the active surface area of an individual semiconductor die. The “oxide ring” of the invention surrounds the guard ring or sealing ring and forms in this manner a mechanical stress release buffer between the sawing paths of the die and the active surface area of the singulated individual semiconductor die.Type: GrantFiled: December 12, 2003Date of Patent: October 2, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Fan Zhang, Bei Chao Zhang, Wuping Liu, Kho Liep Chok, Liang Choo Hsia, Tae Jong Lee, Juan Boon Tan, Xian Bin Wang