Patents by Inventor Wuu-Larng Laih

Wuu-Larng Laih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5736415
    Abstract: A method for manufacturing input/output port devices of a semiconductor circuit having low body effect, suitable for use on a semiconductor substrate on which a plurality of pull-up device regions and pull-down device regions are formed. First, when executing a channel implantation, an anti-punchthrough implantation, and a threshold adjustment implantation, a mask which masks PMOS devices in the CMOS process is used to mask pull-up device regions on a semiconductor substrate. Furthermore, when executing a cell implantation, a mask which masks the outside regions of memory cells is used to mask pull-down device regions. In the invention, the body effect of pull-up devices on the input/output port is reduced without using any extra mask and under the original process, thereby lowering the threshold voltage and reducing the output voltage drop.
    Type: Grant
    Filed: March 4, 1997
    Date of Patent: April 7, 1998
    Assignee: Vanguard International Semiconductor, Corporation
    Inventors: Ming-Chien Chang, Wuu-Larng Laih