Patents by Inventor Wuudiann Ke
Wuudiann Ke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6725432Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: March 23, 2001Date of Patent: April 20, 2004Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6701504Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: January 4, 2001Date of Patent: March 2, 2004Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6698002Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: March 23, 2001Date of Patent: February 24, 2004Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6694501Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: January 4, 2001Date of Patent: February 17, 2004Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6631470Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: March 23, 2001Date of Patent: October 7, 2003Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6629293Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: February 23, 2001Date of Patent: September 30, 2003Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6594800Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: January 4, 2001Date of Patent: July 15, 2003Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Publication number: 20030115564Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: ApplicationFiled: March 23, 2001Publication date: June 19, 2003Applicant: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6574778Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: January 4, 2001Date of Patent: June 3, 2003Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6567957Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: January 4, 2001Date of Patent: May 20, 2003Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Publication number: 20020166098Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: ApplicationFiled: March 23, 2001Publication date: November 7, 2002Applicant: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Publication number: 20020016952Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: ApplicationFiled: January 4, 2001Publication date: February 7, 2002Applicant: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Publication number: 20010042237Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: ApplicationFiled: February 23, 2001Publication date: November 15, 2001Applicant: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Publication number: 20010039641Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: ApplicationFiled: March 23, 2001Publication date: November 8, 2001Applicant: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Publication number: 20010025369Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: ApplicationFiled: January 4, 2001Publication date: September 27, 2001Applicant: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Publication number: 20010018756Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: ApplicationFiled: January 4, 2001Publication date: August 30, 2001Applicant: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Publication number: 20010016933Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: ApplicationFiled: January 4, 2001Publication date: August 23, 2001Applicant: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6269467Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.Type: GrantFiled: September 30, 1999Date of Patent: July 31, 2001Assignee: Cadence Design Systems, Inc.Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
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Patent number: 6108807Abstract: In accordance with the present invention, an apparatus and method for implementing a new user-defined B-S instruction called PINCONTROL is disclosed. When PINCONTROL is in effect, an output pin can be configured to be either driving a constant 0, driving a 1, in the high-impedance (high-Z) state or in the control of system logic; and different pins of the same chips may assume different configurations depending on the content of the capture and update portion of the B-S register. This instruction provides an improved fault insertion capability. For example, if it is desired to inject a stuck-at-0 fault at pin p, pin p can be configured to drive a constant 0 while allowing other pins to function normally. A stuck-at-1 fault can also be injected by configuring pin p to drive a constant 0 while allowing other pins to function normally. An open fault can also be injected by configuring pin p into a high-impedance state.Type: GrantFiled: July 28, 1997Date of Patent: August 22, 2000Assignee: Lucent Technologies Inc.Inventor: Wuudiann Ke
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Patent number: 5841788Abstract: A backplane testing method is provided in which test vectors are applied to individual circuit boards in a system while remaining circuit boards in the system are disabled. The signals on all receivers in the system are observed during testing. The circuit boards are connected to a test bus in a multi-drop arrangement, so that individual circuit boards can be addressed using slave interfaces. A walking enable technique is used to systematically toggle all of the drivers on the circuit boards. An intraboard testing technique is used for applying test vectors including an all 0's vector, an all 1's vector, and a series of test vectors generated from a binary counting sequence. Backplane faults are identified by comparing the observed receiver signals to the signals expected in response to the applied test vectors.Type: GrantFiled: October 18, 1996Date of Patent: November 24, 1998Assignee: Lucent Technologies Inc.Inventor: Wuudiann Ke