Abstract: Provided are a protecting trolley and a construction method of rock burst prewarning protection system in non-contact tunnel construction. The protecting trolley includes a framework, a walking assembly, a rockfall buffering assembly, a spraying assembly and a rock burst prewarning system. The rockfall buffering assembly includes an arch frame in a fixed connection with the framework and a protecting net fixed on the arch frame. The spraying assembly includes a track car in connection with the rockfall buffering assembly and a spraying hose fixed on the track car, and the spraying hose sprays towards the surrounding rock. The rock burst prewarning assembly includes a thermosensitive infrared sensor used for detecting the temperature of the surrounding rock and a highly sensitive laser sensor used for detecting the deformation of the surrounding rock.

Abstract: A method for managing performance and power utilization of a processor in an information handling system (IHS) employing a balanced fully-multithreaded load threshold is disclosed. The method includes providing a maximum current thread utilization (Umax) and a minimum current thread utilization (Umin) among all current thread utilizations of the processor and determining a current performance state (P state) of the processor. The method also includes increasing a current P state of the processor to a next P state of the processor towards a maximum P state (Pmax) of the processor when the current P state of the processor is between Umax and Umin and the current utilization rate of the processor is less than a first threshold utilization rate. The method further includes engaging the processor in a turbo mode when the current P state of the processor reaches the Pmax and the current utilization of the processor is greater than the first threshold utilization rate of the processor.

Abstract: A method for managing performance and power utilization of a processor in an information handling system (IHS) employing a balanced fully-multithreaded load threshold is disclosed. The method includes providing a maximum current thread utilization (Umax) and a minimum current thread utilization (Umin) among all current thread utilizations of the processor and determining a current performance state (P state) of the processor. The method also includes increasing a current P state of the processor to a next P state of the processor towards a maximum P state (Pmax) of the processor when the current P state of the processor is between Umax and Umin and the current utilization rate of the processor is less than a first threshold utilization rate. The method further includes engaging the processor in a turbo mode when the current P state of the processor reaches the Pmax and the current utilization of the processor is greater than the first threshold utilization rate of the processor.

Abstract: A method for managing performance and power utilization of a processor in an information handling system (IHS) employing a balanced fully-multithreaded load threshold is disclosed. The method includes providing a maximum current thread utilization (Umax) and a minimum current thread utilization (Umin) among all current thread utilizations of the processor and determining a current performance state (P state) of the processor. The method also includes increasing a current P state of the processor to a next P state of the processor towards a maximum P state (Pmax) of the processor when the current P state of the processor is between Umax and Umin and the current utilization rate of the processor is less than a first threshold utilization rate. The method further includes engaging the processor in a turbo mode when the current P state of the processor reaches the Pmax and the current utilization of the processor is greater than the first threshold utilization rate of the processor.

Abstract: A method for managing performance and power utilization of a processor in an information handling system (IHS) employing a balanced fully-multithreaded load threshold is disclosed. The method includes providing a maximum current thread utilization (Umax) and a minimum current thread utilization (Umin) among all current thread utilizations of the processor and determining a current performance state (P state) of the processor. The method also includes increasing a current P state of the processor to a next P state of the processor towards a maximum P state (Pmax) of the processor when the current P state of the processor is between Umax and Umin and the current utilization rate of the processor is less than a first threshold utilization rate. The method further includes engaging the processor in a turbo mode when the current P state of the processor reaches the Pmax and the current utilization of the processor is greater than the first threshold utilization rate of the processor.

Abstract: A method for managing performance and power utilization of a processor in an information handling system (IHS) employing a balanced fully-multithreaded load threshold includes providing a maximum current thread utilization (Umax) and a minimum current thread utilization (Umin) among all current thread utilizations of the processor and determining a current performance state (P state) of the processor. The method also includes increasing a current P state of the processor to a next P state of the processor towards a maximum P state (Pmax) of the processor when the current P state of the processor is between Umax and Umin and the current utilization rate of the processor is less than a first threshold utilization rate. The method further includes engaging the processor in a turbo mode when the current P state of the processor reaches the Pmax and the current utilization of the processor is greater than the first threshold utilization rate of the processor.

Abstract: A method for managing performance and power utilization of a processor in an information handling system (IHS) employing a balanced fully-multithreaded load threshold is disclosed. The method includes providing a maximum current thread utilization (Umax) and a minimum current thread utilization (Umin) among all current thread utilizations of the processor and determining a current performance state (P state) of the processor. The method also includes increasing a current P state of the processor to a next P state of the processor towards a maximum P state (Pmax) of the processor when the current P state of the processor is between Umax and Umin and the current utilization rate of the processor is less than a first threshold utilization rate. The method further includes engaging the processor in a turbo mode when the current P state of the processor reaches the Pmax and the current utilization of the processor is greater than the first threshold utilization rate of the processor.

Abstract: A method for dynamically adjusting performance states of a processor includes executing a workload associated with a workload mode and determining a primary thread among all processor threads executing the workload. The method also includes calculating and setting a performance state (P state) of the processor based on the workload mode.

Abstract: System and methods for preventing an operating-system scheduler in a computer system from crashing as a result of an uncleared periodic interrupt are disclosed. A periodic interrupt is generated using a real-time clock (RTC) residing on a chipset. A flag indicating a periodic interrupt is entered into a status register associated with the RTC in firmware residing on the CMOS chip, if the status register indicates no periodic interrupt has been pending. An interrupt handler associated with the RTC attempts to handle the periodic interrupt, if pending. If the periodic interrupt is pending after a preset interval of time elapses, a basic-input-output system (BIOS) residing on a memory unit coupled to the chipset generates a system-management interrupt (SMI). If the periodic interrupt is pending after the preset interval of time elapses, a firmware SMI handler residing on the memory unit clears the pending periodic interrupts from the status register.

Abstract: A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a system management interrupt. The primary processor will write a reason code to a storage location and set a watchdog timer, the expiration of which causes all of the processors of the system to enter a system management mode. After all of the processors have entered system management mode, it is determined if the reason code of the storage location corresponds to certain software-based system management interrupts. If so, the system management interrupt is handled by the local processors. Following the handling of the system management interrupt by the local processor, a signal is sent to each of the other processors to cause the processors to exit system management mode.

Abstract: A system and method is disclosed for enumerating multi-level processor-memory affinities for non-uniform memory access systems. A processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in an information-handling system is calculated using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system. The information-handling system then performs an algorithm on each processor-memory affinity hierarchy to obtain processor-memory affinity values in the information-handling system, and populates a table using the processor-memory affinity values. An operating system in the information-handling system can use the table to allocate memory units among microprocessors in the information-handling system.

Abstract: A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a system management interrupt. The primary processor will write a reason code to a storage location and set a watchdog timer, the expiration of which causes all of the processors of the system to enter a system management mode. After all of the processors have entered system management mode, it is determined if the reason code of the storage location corresponds to certain software-based system management interrupts. If so, the system management interrupt is handled by the local processors. Following the handling of the system management interrupt by the local processor, a signal is sent to each of the other processors to cause the processors to exit system management mode.

Abstract: A system and method is disclosed in which, during the execution of an interrupt handling sequence in one of the processor of a multiprocessor system, a processors write a reason code to a status register to identify the cause of the interrupt. The BIOS code of the system writes to an interrupt initiation register to cause each of the processors to enter an interrupt handling sequence. Each of the processors of the system handling the interrupt on the basis of the content of the status register, resulting in each of the processors synchronously handling an interrupt for an event that would otherwise result in a local interrupt.

Abstract: During power-on self-test (POST) the basic input-output operating system (BIOS) may set hot-add status light emitting diodes (LEDs) to appropriate colors so as to indicate which memory slot(s) is most optimal for hot-adding a hot-plug memory module. In the case where the user or administrator fails to notice or understand the meaning of the LED color representation when hot-adding the new memory module, the BIOS Service Management Initiative (SMI) handler (which controls the hot-add to the information handling system) will verify if the hot-add memory module is being installed into an optimal memory slot. If not, the BIOS may capture a Chassis System Event Log (SEL) indicating a non-optimal Hot-add and may flash a front panel LED to a certain color, e.g., amber, and may also issue an appropriate error message. Additional Advanced Configuration and Power Interface (ACPI) implementations may be used for a more user-friendly alert and/or message display.

Abstract: System and methods for preventing an operating-system scheduler in a computer system from crashing as a result of an uncleared periodic interrupt are disclosed. A periodic interrupt is generated using a real-time clock (RTC) residing on a chipset. A flag indicating a periodic interrupt is entered into a status register associated with the RTC in firmware residing on the CMOS chip, if the status register indicates no periodic interrupt has been pending. An interrupt handler associated with the RTC attempts to handle the periodic interrupt, if pending. If the periodic interrupt is pending after a preset interval of time elapses, a basic-input-output system (BIOS) residing on a memory unit coupled to the chipset generates a system-management interrupt (SMI). If the periodic interrupt is pending after the preset interval of time elapses, a firmware SMI handler residing on the memory unit clears the pending periodic interrupts from the status register.

Abstract: A system and method is disclosed for enumerating multi-level processor-memory affinities for non-uniform memory access systems. A processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in an information-handling system is calculated using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system. The information-handling system then performs an algorithm on each processor-memory affinity hierarchy to obtain processor-memory affinity values in the information-handling system, and populates a table using the processor-memory affinity values. An operating system in the information-handling system can use the table to allocate memory units among microprocessors in the information-handling system.

Abstract: A system and method for notifying an operating system of an error signal transmitted by a communications medium is disclosed. The communications medium connects a plurality of electronic devices. The operating system includes device drivers and is capable of configuring communications between one or more applications and the communications medium. A detector is coupled to the communications medium. The detector receives error signals transmitted by the communications medium, one or more error signals associated with one of the electronic devices. A BIOS is coupled to the detector. The BIOS is capable of determining an electronic device associated with a first error signal. The BIOS generates a hot-eject signal identifying that electronic device in response to the first error signal. The operating system blocks communications between the applications and the identified electronic device in response to the BIOS generating the hot-eject signal.

Abstract: A system and method for notifying an operating system of an error signal transmitted by a communications medium is disclosed. The communications medium connects a plurality of electronic devices. The operating system includes device drivers and is capable of configuring communications between one or more applications and the communications medium. A detector is coupled to the communications medium. The detector receives error signals transmitted by the communications medium, one or more error signals associated with one of the electronic devices. A BIOS is coupled to the detector. The BIOS is capable of determining an electronic device associated with a first error signal. The BIOS generates a hot-eject signal identifying that electronic device in response to the first error signal. The operating system blocks communications between the applications and the identified electronic device in response to the BIOS generating the hot-eject signal.