Patents by Inventor Wuyang ZHAO

Wuyang ZHAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10944073
    Abstract: The present application discloses a display panel having a display area and a peripheral area. The display panel includes a base substrate; a display unit on the base substrate; an encapsulating layer on a side of the display unit distal to the base substrate and encapsulating the display unit; and a first crack barrier layer on the base substrate and in the peripheral area and forming a first enclosure substantially surrounding a first area. The encapsulating layer includes a first inorganic sub-layer. The first inorganic sub-layer includes a first part enclosed inside the first area by the first crack barrier layer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 9, 2021
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Weiyun Huang, Zhenxiao Tong, Wuyang Zhao, Youngyik Ko
  • Publication number: 20200127228
    Abstract: The present application discloses a display panel having a display area and a peripheral area. The display panel includes a base substrate; a display unit on the base substrate; an encapsulating layer on a side of the display unit distal to the base substrate and encapsulating the display unit; and a first crack barrier layer on the base substrate and in the peripheral area and forming a first enclosure substantially surrounding a first area. The encapsulating layer includes a first inorganic sub-layer. The first inorganic sub-layer includes a first part enclosed inside the first area by the first crack barrier layer.
    Type: Application
    Filed: December 5, 2017
    Publication date: April 23, 2020
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Weiyun Huang, Zhenxiao Tong, Wuyang Zhao, Youngyik Ko
  • Patent number: 9564354
    Abstract: The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes: forming a structure for via-hole etching, includes: a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away the remaining thickness of the gate insulating layer, and uncovering the low-temperature poly-silicon layer; removing the mask layer to form a via-hole structure.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: February 7, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Byung Chun Lee, Donghua Jiang, Yongyi Fu, Wuyang Zhao, Chundong Li
  • Publication number: 20150303099
    Abstract: The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes: forming a structure for via-hole etching, includes: a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away the remaining thickness of the gate insulating layer, and uncovering the low-temperature poly-silicon layer; removing the mask layer to form a via-hole structure.
    Type: Application
    Filed: December 3, 2013
    Publication date: October 22, 2015
    Inventors: Byung Chun LEE, Donghua JIANG, Yongyi FU, Wuyang ZHAO, Chundong LI
  • Patent number: D747984
    Type: Grant
    Filed: August 30, 2014
    Date of Patent: January 26, 2016
    Assignees: Sensoro Co. Ltd.
    Inventors: Wuyang Zhao, Ruojiao Zhang, Xin Zheng, Xiaofei Yuan, Mingming Zhang