Abstract: The present application provides a structure and method for improving near-infrared quantum efficiency of a backside illuminated image sensor. The structure includes a substrate and a plurality of photodiodes. The photodiodes are formed in the substrate. A cell deep trench isolation structure is fabricated on a surface of each photodiode. The cross section of the cell deep trench isolation structure 3 parallel to the surface of said photodiode comprises one or both of a four-quadrant square shape and a Union Jack shape. In the present application, by fabricating the cell deep trench isolation structures on the surface of each photodiode, the cell deep trench isolation structures increase light scattering in the photodiode, thus the optical path is increased, thereby improving the absorption of incident light, especially in near-infrared wavelength. As a result the quantum efficiency and sensor's imaging quality are improved.

Abstract: The present invention provides a pixel structure for a CMOS image sensor and a manufacturing method therefor, the pixel structure comprising: a substrate; a floating diffusion region formed in the substrate; an interlayer dielectric layer formed on an upper surface of the substrate and covering the pixel structure; and a light-shielding wall formed in the interlayer dielectric layer, wherein a projection of the light-shielding wall in the height direction of the substrate surrounds a projection of the floating diffusion region in the height direction of the substrate. The present invention further provides a manufacturing method for manufacturing the pixel structure. The pixel structure manufactured by means of the manufacturing method provided in the present invention can shield the irradiation of incident light on the floating diffusion region of the global CMOS image sensor, thereby reducing interference signals.

Abstract: The present invention provides a pixel structure for a CMOS image sensor and a manufacturing method therefor, the pixel structure comprising: a substrate; a floating diffusion region formed in the substrate; an interlayer dielectric layer formed on an upper surface of the substrate and covering the pixel structure; and a light-shielding wall formed in the interlayer dielectric layer, wherein a projection of the light-shielding wall in the height direction of the substrate surrounds a projection of the floating diffusion region in the height direction of the substrate. The present invention further provides a manufacturing method for manufacturing the pixel structure. The pixel structure manufactured by means of the manufacturing method provided in the present invention can shield the irradiation of incident light on the floating diffusion region of the global CMOS image sensor, thereby reducing interference signals.

Abstract: TSV layout structure and TSV interconnect structure, and their fabrication methods are provided. An exemplary TSV interconnect structure includes a semiconductor substrate having a first region and a second region; and a plurality of through-holes disposed in the first region and the second region of the semiconductor substrate. An average through-hole density of the first region is greater than an average through-hole density of the entire semiconductor substrate. The average through-hole density of the entire semiconductor substrate is less than or equal to about 2%. A metal layer having a planarized surface is filled in the plurality of through-holes in the semiconductor substrate.

Abstract: TSV layout structure and TSV interconnect structure, and their fabrication methods are provided. An exemplary TSV interconnect structure includes a semiconductor substrate having a first region and a second region; and a plurality of through-holes disposed in the first region and the second region of the semiconductor substrate. An average through-hole density of the first region is greater than an average through-hole density of the entire semiconductor substrate. The average through-hole density of the entire semiconductor substrate is less than or equal to about 2%. A metal layer having a planarized surface is filled in the plurality of through-holes in the semiconductor substrate.