Abstract: Embodiments described herein provide a method for waking a first node in a low power mode. A network comprises at least the first node and a second node in an awake mode where the first and second nodes have respective transceivers coupled via substantially fixed communication pathways. The transceiver of the second node obtains a training signal designed to be transmitted at a pre-defined symbol rate and transmits the training signal at a symbol rate lower than the pre-defined symbol rate to the physical layer of the first node for a predetermined duration of time. The second node, in response to receiving the training signal transitions from the low power mode to an awake state.

Abstract: Embodiments described herein provide a method for waking a first node in a low power mode. A network comprises at least the first node and a second node in an awake mode where the first and second nodes have respective transceivers coupled via substantially fixed communication pathways. The transceiver of the second node obtains a training signal designed to be transmitted at a pre-defined symbol rate and transmits the training signal at a symbol rate lower than the pre-defined symbol rate to the physical layer of the first node for a predetermined duration of time. The second node, in response to receiving the training signal transitions from the low power mode to an awake state.

Abstract: A successive-approximation register (SAR) analog-to-digital converter (ADC) includes a SAR circuit configured to generate a digital code based on an analog input signal. A digital-to-analog converter (DAC) is configured to convert the digital code to an analog voltage. The SAR circuit is further configured to generate a digital output signal based on a comparison between the analog input signal and the analog voltage. A first capacitor is configured to provide a reference voltage to the DAC. An adaptive charging module is configured to stabilize the reference voltage provided to the DAC by selectively connecting to a supply voltage during a first operating phase of the ADC to store a charge in the adaptive charging module and selectively connecting to the first capacitor during a second operating phase of the ADC to combine the charge stored in the adaptive charging module with a charge of the first capacitor.

Abstract: A voltage regulator includes a supply filter, a bias filter, and first and second circuits. The supply filter is configured to operate from a supply voltage, and to generate a filtered supply voltage at a first node. The supply filter includes a transistor and a capacitor. First and control terminals of the transistor receive the supply voltage. A second terminal of the transistor and a first terminal of the capacitor are connected to the first node. The first circuit is configured to operate from both the supply voltage and the filtered supply voltage, and to generate a second reference voltage based on an input reference voltage. The bias filter is configured to generate a filtered second reference voltage based on the second reference voltage. The second circuit is configured to operate from the filtered supply voltage, and to generate a regulated voltage based on the filtered second reference voltage.

Abstract: A voltage regulator includes a master circuit, first and second filters, and a slave circuit. The master circuit provides a second reference voltage based on a first reference voltage and a supply voltage. The first filter provides a filtered second reference voltage based on the second reference voltage. The second filter provides a filtered supply voltage based on the supply voltage. The slave circuit provides a third reference voltage based on the filtered second reference voltage and the filtered supply voltage. The second filter includes an NMOS transistor and a capacitor. The gate and the drain of the NMOS transistor receive the supply voltage. A first terminal of the capacitor is electrically coupled to a source of the NMOS transistor. A second terminal of the capacitor is electrically coupled to ground. The source of the NMOS transistor provides the filtered supply voltage.

Abstract: Relay circuitry for a power-over-network device is provided. The relay circuitry allows power-supplying network devices to identify and subsequently to supply power across a network connection to the power-over-network device, thereby eliminating the need for external power sources. The relay circuitry is operative using only the signals transmitted along a data line across the network connection. The relay circuitry is integrated together with switching circuitry on-chip on the power-over-network device. The relay circuitry and switching circuitry are further designed to propagate both the test signals and the subsequent data signals prior to and after the turning on of the power-over-network device, respectively, with minimal signal degradation.

Abstract: Relay circuitry for a power-over-network device is provided. The relay circuitry allows power-supplying network devices to identify and subsequently to supply power across a network connection to the power-over-network device, thereby eliminating the need for external power sources. The relay circuitry is operative using only the signals transmitted along a data line across the network connection. The relay circuitry is integrated together with switching circuitry on-chip on the power-over-network device. The relay circuitry and switching circuitry are further designed to propagate both the test signals and the subsequent data signals prior to and after the turning on of the power-over-network device, respectively, with minimal signal degradation.