Abstract: A system provides a uniform delay in crossovers in opposite directions of a variable input voltage relative to a reference voltage. A comparator is included for producing first and second comparison voltages in accordance with the relative magnitudes of the input and reference voltages. A clamping circuit provides first and second clamping voltages. A control circuit produces first and second control voltages dependent upon the individual occurrences of the first and second comparison voltages. The first control voltage is greater by a particular magnitude than the first clamping voltage. The second control voltage is less than the second clamping voltage by the particular magnitude.

Abstract: An integrated circuit memory system having an array of ECL memory cells, an address circuit, a READ/WRITE circuit and a coupling circuit which increases the operating current of an addressed memory cell during a READ/WRITE operation. The increased operating current is short enough to prevent an excessive saturation of the memory cell transistors. The addressed memory cells remain in a low operating current sufficient to maintain the memory cells in their particular states. Since timing is critical, timing circuits for a system clock are also part of the memory system.