Abstract: The present disclosure relates to certain (2S)—N-[(1S)-1-cyano-2-phenylethyl]-1,4-oxazepane-2-carboxamide compounds (including pharmaceutically acceptable salts thereof), that inhibit dipeptidyl peptidase 1 (DPP1) activity, to their utility in treating and/or preventing clinical conditions including respiratory diseases, such as asthma and chronic obstructive pulmonary disease (COPD), to their use in therapy, to pharmaceutical compositions containing them and to processes for preparing such compounds.

Abstract: A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for storing the difference signal over time. The SDM may have a control input coupled to the buffer. The adder may have inputs coupled to the SDM and a source of an integer control word. The first frequency divider may have an input for receiving an external clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the external clock signal divided by (N+F/M).

Abstract: A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for accumulating the difference signal over time. The sigma-delta modulator (SDM) may have a control input coupled to the buffer. The adder may have inputs coupled to the (SDM) and a source of an integer control word. The first frequency divider may have an input for a clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the input clock signal divided by (N+F/M), wherein N is determined by the integer control word and F/M is determined by an output of the SDM.

Abstract: A phase-locked loop frequency synthesizer has a charge pump, phase-locked loop filter, voltage-controlled oscillator, and a bandwidth calibration circuit. The bandwidth calibration circuit measures the gain of the voltage-controlled oscillator and uses the measured voltage-controlled oscillator gain to adjust the charge pump level. The charge pump level is adjusted so that a product of the voltage-controlled oscillator gain and the measured charge pump level results in a constant phase-locked loop bandwidth.

Abstract: A write precompensation circuit includes a plurality of current-controlled delay buffers connected to form a delay line having selectable output taps. The precise delay of each delay buffer is controllable by a secondary control current derived from a master control current such that the precise delay is a precise percent of an oscillator period. The master control current is also used to control the period of a master write clock generated by a current-controlled ring oscillator of delay buffers. A write precompensation method includes steps of controlling current in delay buffers in a current-controlled ring oscillator used to generate a master write clock and current in delay buffers in a current-controlled delay line to maintain delays through delay buffers of the oscillator and the delay line in predetermined proportions to each other.

Abstract: A charge pump system for charging an integrating capacitor includes a current source for supplying a first current of a first polarity, a second current of the opposite polarity which is a fraction of the first current, a third current of the opposite polarity, and a fourth current of the first polarity which is a fraction of the third current, and a switching device for simultaneously interconnecting both the first and second currents to the integrating capacitor to provide a first pump down charging current which is the fractional difference between the first and second currents, and also alternately selectively interconnecting both the third and fourth currents to the integrating capacitor to provide a second pump up charging current which is a fractional difference between the third and fourth currents and opposite in polarity to the first charging current.

Abstract: An intrinsic R2R resistance ladder digital to analog converter (DAC) includes a plurality of matched semiconductor ladder switches, one in each of the R and 2R legs of the R2R ladder. The ON resistance of each semiconductor switch being matched to constitute the resistance ladder of the DAC; the ladder switches being operated in response to the digital signal input to the DAC; a reference circuit including a reference semiconductor switch matched with the ladder switches responsive to a reference current to generate a reference voltage; and a voltage follower circuit for monitoring the reference voltage and adjusting the current through the ladder switches to match the voltage at each ladder switch with the reference voltage for precisely fixing the DAC analog output current as a proportion of the reference current in dependence upon the operation of the ladder switches by the digital input signal.

Abstract: A hybrid analog/digital automatic gain control gain recovery system includes a variable gain amplifier (VGA) for receiving a variable amplitude input signal; a first AGC loop includes an analog to digital converter (DAC) for receiving the analog input signal and converting it to a digital signal; a digital gain error detection circuit for detecting variations of the digital signal in a first range and generating a digital error correction signal; and a digital to analog converter (DAC) for converting the digital error correction signal to a first analog correction signal; a second analog AGC loop includes an analog gain error detection circuit, responsive to variations in the output of the VGA in a second range greater than the first range for generating a second analog correction signal; and an integrator circuit responsive to the first and second analog correction signals for providing to the VGA a control signal to adjust the gain of the VGA to accommodate variations in the input signal amplitude.