Abstract: The invention concerns a module comprising a carrier element, a semiconductor device mounted on said carrier element and a silicon-based insulating layer. The silicon-based insulating layer is arranged on the side of the carrier element opposite to the semiconductor device. The invention further concerns a module comprising a semiconductor device, a mold compound at least partly covering the semiconductor device and a silicon-based passivation layer. The silicon-based passivation layer covers at least partly the periphery of the mold compound.

Abstract: A semiconductor module and a method for producing the same is disclosed. One embodiment provides that an intermediate element has been or is formed, which has been or is formed for making electrical contact materially between a contact region provided and a connection region provided and in direct material and electrical contact with and for area adaptation between these.

Abstract: A power semiconductor component stack, using lead technology with surface-mountable external contacts, includes at least two MOSFET power semiconductor components each having a top side and an underside. The underside includes: a drain external contact area, a source external contact area and a gate external contact area. The top side includes at least one source external contact area and a gate external contact area. The gate external contact areas on the top side and the underside are electrically connected to one another. The power semiconductor component stack is a series circuit or a parallel circuit of MOSFET power semiconductor components arranged one above another in a plastic housing composition.

Abstract: A semiconductor device includes a vertical transistor and an external contact plane. The transistor includes: a first side with a first load electrode and a control electrode, and an opposite second side with a second load electrode. The first side of the transistor faces the external contact plane. A dielectric layer extends from at least one edge side of the transistor as far as the second load terminal. An electrically conductive deposited layer is arranged on the dielectric layer and electrically connects the second load electrode to the second load terminal.

Abstract: A semiconductor component has a leadframe, a semiconductor die and an encapsulation element. The leadframe has a die pad having a first side, at least one lead spaced at a distance from the die pad and at least one support bar remnant protruding from the die pad, each having a distal end. The encapsulation element has plastic and encapsulates at least the semiconductor die and a portion of the first side of the die pad. At least one support bar remnant is positioned within the encapsulation element and the distal end of the support bar remnant is encapsulated by at least one dielectric compound.

Abstract: Embodiments of apparatus, having a plastic structure, a semiconductor chip at least partially embedded in the structure; a heat sink at least partially embedded in the structure with a portion thereof projecting from the structure; and a bridge member, at least partially embedded in the structure and thermally coupling the semiconductor chip to the heat sink.

Abstract: A connection structure includes a semiconductor die having a first major surface and an electrically conductive substrate having a second major surface. At least part of the second major surface is positioned facing towards and spaced at a distance from the first major surface. A galvanically deposited metallic layer extends between the first major surface and the second major surface and electrically connects the first major surface and the second major surface.

Abstract: A power semiconductor component (2) has a semiconductor body with a front face (7) and a rear face (9). The front face (7) has a front-face metallization (8), which provides at least one first contact pad (11). A structured metal seed layer (14) is provided as the front-face metallization (8), is arranged directly on the semiconductor body, and has a thickness d, where 1 nm?d?0.5 ?m.

Abstract: A power semiconductor device has a first chip carrier part (11) and a second chip carrier part (12), the first chip carrier part (11) and the second chip carrier part (12) being spaced apart from one another and being electrically conductive in each case. A first chip with a power transistor is arranged on the first chip carrier part (11) and a second chip (14) is arranged on the second chip carrier part (12). The terminal for a first potential (DC?) of a supply voltage is electrically connected to the first chip (13) via the first chip carrier part and the terminal for the second potential of a supply voltage (DC+) is electrically connected to the second chip (14) via the second chip carrier part.

Abstract: A semiconductor device (1; 25) has a vertical semiconductor component (2), a first metalization (8) and a second metalization (13). The second metalization (13) has an integral film with a first end (14) with a first contact area (17), an intermediate region (15) and a second end (16) with a second contact area (19). The first contact area (17) is arranged on the rear side (6) of the semiconductor component (2) and the second contact area (19) is essentially arranged in the plane of the external contact area (12) of the first metalization (8) and provides an external contact area (12). The first contact area (17) and the second contact area (19) are arranged on opposite surfaces of the film of the second metalization (13).

Abstract: A power semiconductor component (30) with power semiconductor chip stack (14) has a base power semiconductor chip (16) and a power semiconductor chip (17) stacked on the rear side of the base power semiconductor chip (16), a rewiring structure for the electrical coupling of the power semiconductor chips being arranged within the rear side metallization.

Abstract: An electronic component has a housing and at least two terminal pins protruding out from a first side face of the housing. The housing has an isolation barrier formed between the at least two terminal pins. The isolation barrier extends the leakage path between two neighboring terminal pins and consequently increases the dielectric strength.

Abstract: The invention relates to a two-chip power IC, in which a sensor chip having a sensor is mounted on a switch chip having a switch. The sensor is electrically connected to the switch in order to turn the switch off when a temperature detected by the sensor exceeds a threshold value which can be preset. In order to ensure that the sensor chip is heated more quickly, at least one supply line for the switch is routed in the vicinity of the sensor so as to assure good heat transfer from the supply line to the sensor.

Abstract: A bearer strip having components arranged in several parallel rows with variable spacing between the rows so as to increase packing density while providing sufficient empty space for introducing free flowing plastic on the bearer strip.

Abstract: A semiconductor component includes an insulating housing. A plurality of sheet-metal mounting plates are disposed in one and the same plane and are electrically separated from one another in the housing. Semiconductor switches of a rectifier bridge are electrically conductively secured to the mounting plates. Sheet-metal connection leads are electrically connected to the semiconductor switches. At least one sheet-metal connection lead is electrically connected to the mounting plates.