Patents by Inventor Xaver Schlogel

Xaver Schlogel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230230903
    Abstract: A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side. The contact portion is configured to be attached to an electrically conductive structure by a die attach material, a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion.
    Type: Application
    Filed: December 21, 2022
    Publication date: July 20, 2023
    Applicant: Infineon Technologies AG
    Inventors: Hooi Boon TEOH, Hao ZHUANG, Oliver BLANK, Paul Armand CALO, Markus DINKEL, Josef Höglauer, Daniel Hölzl, Wee Aun JASON LIM, Gerhard Thomas Nöbauer, Ralf OTREMBA, Martin Pölzl, Ying Pok SAM, Xaver Schlögel, Chee Voon TAN
  • Patent number: 10109609
    Abstract: A connection structure is provided that includes a semiconductor substrate, a first layer arranged on the semiconductor substrate, the first layer being configured to provide shielding against radioactive rays, a second layer arranged on the first layer, the second layer including solder including Pb, and an electrically conductive member arranged on the second layer.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 23, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Patent number: 9196554
    Abstract: An electronic component includes at least one semiconductor device and a redistribution board comprising at least two nonconductive layers and a conductive redistribution structure. The semiconductor device is embedded in the redistribution board and electrically coupled to the redistribution structure and the redistribution board has a side face with a step. An outer contact pad of the redistribution structure is arranged on the step.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: November 24, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Patent number: 9196577
    Abstract: A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: November 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Publication number: 20150200178
    Abstract: A connection structure is provided that includes a semiconductor substrate, a first layer arranged on the semiconductor substrate, the first layer being configured to provide shielding against radioactive rays, a second layer arranged on the first layer, the second layer including solder including Pb, and an electrically conductive member arranged on the second layer.
    Type: Application
    Filed: January 13, 2014
    Publication date: July 16, 2015
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Publication number: 20150194373
    Abstract: A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 9, 2015
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Publication number: 20150091176
    Abstract: An electronic component includes at least one semiconductor device and a redistribution board comprising at least two nonconductive layers and a conductive redistribution structure. The semiconductor device is embedded in the redistribution board and electrically coupled to the redistribution structure and the redistribution board has a side face with a step. An outer contact pad of the redistribution structure is arranged on the step.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Patent number: 6776663
    Abstract: An electronic component has a housing and at least two terminal pins protruding out from a first side face of the housing. The housing has an isolation barrier formed between the at least two terminal pins. The isolation barrier extends the leakage path between two neighboring terminal pins and consequently increases the dielectric strength.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: August 17, 2004
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Xaver Schlögel
  • Publication number: 20020094710
    Abstract: An electronic component has a housing and at least two terminal pins protruding out from a first side face of the housing. The housing has an isolation barrier formed between the at least two terminal pins. The isolation barrier extends the leakage path between two neighboring terminal pins and consequently increases the dielectric strength.
    Type: Application
    Filed: November 8, 2001
    Publication date: July 18, 2002
    Inventors: Ralf Otremba, Xaver Schlogel
  • Patent number: 6323531
    Abstract: The invention relates to a two-chip power IC, in which a sensor chip having a sensor is mounted on a switch chip having a switch. The sensor is electrically connected to the switch in order to turn the switch off when a temperature detected by the sensor exceeds a threshold value which can be preset. In order to ensure that the sensor chip is heated more quickly, at least one supply line for the switch is routed in the vicinity of the sensor so as to assure good heat transfer from the supply line to the sensor.
    Type: Grant
    Filed: January 3, 2000
    Date of Patent: November 27, 2001
    Assignee: Infineon Technologies AG
    Inventors: Rainald Sander, Xaver Schlögel, Jenoe Tihanyi
  • Patent number: 6271584
    Abstract: A bearer strip having components arranged in several parallel rows with variable spacing between the rows so as to increase packing density while providing sufficient empty space for introducing free flowing plastic on the bearer strip.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: August 7, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventors: Stefan Schmausser, Otto Gruber, Siegfried Fischer, Walter Juri, Bernd Barchmann, Jürgen Winterer, Martin Petz, Jürgen Steinbichler, Xaver Schlögel, Otto Voggenreiter