Patents by Inventor Xavier Brun
Xavier Brun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113005Abstract: Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Jeremy Ecton, Aleksandar Aleksov, Hiroki Tanaka, Brandon Marin, Srinivas Pietambaram, Xavier Brun
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Publication number: 20240063071Abstract: Multi-die composite structures including a multi-layered inorganic dielectric gap fill material within a space between adjacent IC dies. A first layer of fill material with an inorganic composition may be deposited over IC dies with a high-rate deposition process, for example to at least partially fill a space between the IC dies. The first layer of fill material may then be partially removed to modify a sidewall slope of the first layer or otherwise reduce an aspect ratio of the space between the IC dies. Another layer of fill material may be deposited over the lower layer of fill material, for example with the same high-rate deposition process. This dep-etch-dep cycle may be repeated any number of times to backfill spaces between IC dies. The multi-layer fill material may then be globally planarized and the IC die package completed and/or assembled into a next-level of integration.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Jeffery Bielefeld, Adel Elsherbini, Bhaskar Jyoti Krishnatreya, Feras Eid, Gauri Auluck, Kimin Jun, Mohammad Enamul Kabir, Nagatoshi Tsunoda, Renata Camillo-Castillo, Tristan A. Tronic, Xavier Brun
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Publication number: 20240063142Abstract: Multi-die packages including IC die crack mitigation features. Prior to the bonding of IC dies to a host substrate, the IC dies may be shaped, for example with a corner radius or chamfer. After bonding the shaped IC dies, a fill comprising at least one inorganic material may be deposited over the IC dies, for example to backfill a space between adjacent IC dies. With the benefit of a greater IC die sidewall slope and/or smoother surface topology associated with the shaping process, occurrences of stress cracking within the fill and concomitant damage to the IC dies may be reduced. Prior to depositing a fill, a barrier layer may be deposited over the IC die to prevent cracks that might form in the fill material from propagating into the IC die.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel Elsherbini, Wenhao Li, Bhaskar Jyoti Krishnatreya, Tushar Talukdar, Botao Zhang, Yi Shi, Haris Khan Niazi, Feras Eid, Nagatoshi Tsunoda, Xavier Brun, Mohammad Enamul Kabir, Omkar Karhade, Shawna Liff, Jiraporn Seangatith
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Publication number: 20240063089Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die and an inorganic dielectric material adjacent the integrated circuit dies and over the base die. The multichip composite device includes a dummy die, dummy vias, or integrated fluidic cooling channels laterally adjacent the integrated circuit dies to conduct heat from the base die.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel Elsherbini, Wenhao Li, Bhaskar Jyoti Krishnatreya, Debendra Mallik, Krishna Vasanth Valavala, Lei Jiang, Yoshihiro Tomita, Omkar Karhade, Haris Khan Niazi, Tushar Talukdar, Mohammad Enamul Kabir, Xavier Brun, Feras Eid
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Publication number: 20240063076Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die, a conformal thermal heat spreading layer on the top and sidewalls of the integrated circuit dies, and an inorganic dielectric material on a portion of the conformal thermal heat spreading layer, laterally adjacent the integrated circuit dies, and over the base die. The conformal thermal heat spreading layer includes a high thermal conductivity material to provide a thermal pathway for the integrated circuit dies during operation.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Mohammad Enamul Kabir, Bhaskar Jyoti Krishnatreya, Kimin Jun, Adel Elsherbini, Tushar Talukdar, Feras Eid, Debendra Mallik, Krishna Vasanth Valavala, Xavier Brun
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Publication number: 20240063147Abstract: Techniques and mechanisms to mitigate corrosion to via structures of a composite chiplet. In an embodiment, a composite chiplet comprises multiple integrated circuit (IC) components which are each in a different respective one of multiple levels. One or more conductive vias extend through an insulator layer in a first level of the multiple levels. An annular structure of the composite chiplet extends vertically through the insulator layer, and surrounds the one or more conductive vias in the insulator layer. The annular structure mitigates an exposure of the one or more conductive vias to moisture which is in a region of the insulator layer that is not surrounded by the annular structure. In another embodiment, the annular structure further surrounds an IC component which extends in the insulator layer.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel Elsherbini, Mohammad Enamul Kabir, Johanna Swan, Omkar Karhade, Kimin Jun, Feras Eid, Shawna Liff, Xavier Brun, Bhaskar Jyoti Krishnatreya, Tushar Talukdar, Haris Khan Niazi
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Publication number: 20240063091Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel Elsherbini, Feras Eid, Scot Kellar, Yoshihiro Tomita, Rajiv Mongia, Kimin Jun, Shawna Liff, Wenhao Li, Johanna Swan, Bhaskar Jyoti Krishnatreya, Debendra Mallik, Krishna Vasanth Valavala, Lei Jiang, Xavier Brun, Mohammad Enamul Kabir, Haris Khan Niazi, Jiraporn Seangatith, Thomas Sounart
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Publication number: 20240063136Abstract: An integrated circuit (IC) device comprises an array comprising rows and columns of conductive interconnect pads. At least one optical alignment fiducial region is distinct from the array and comprises a fiducial pattern, wherein the fiducial pattern comprises a first group of pads contiguous to a second group of pads, and wherein a width of a space between nearest pads of the first and second groups is wider than the spaces between pads within each group.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Haris Khan Niazi, Yi Shi, Adel Elsherbini, Xavier Brun, Georgios Dogiamis, Thomas Brown, Omkar Karhade
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Publication number: 20230317546Abstract: Embodiments are directed to a device having an overhang portion. In some embodiments, a main body structure of the device comprises an IC die and an exterior surface of the main body structure comprises the overhang portion. The overhang portion adjoins a sidewall structure of the main body structure of the device, which is substantially perpendicular to a backside of the IC die. In some embodiments, the main body structure further comprises a package mold structure, which comprises the overhang portion.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Xavier Brun, Nabankur Deb, Feras Eid
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Publication number: 20230317549Abstract: A porous mesh structure for use in the thermal management of integrated circuit devices may be formed as a solid matrix with a plurality of pores dispersed therein, wherein the solid matrix may be a plurality of fused matrix material particles and the plurality of pores may comprise between about 10% and 90% of a volume of the porous mesh structure. The porous mesh structure may be formed on an integrated circuit device and/or on a heat dissipation assembly component, and may be incorporated into an immersion cooling assembly, wherein the porous mesh structure may act as a nucleation site for a working fluid in the immersion cooling assembly.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Feras Eid, Wenhao Li, Paul Diglio, Xavier Brun, Johanna Swan
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Patent number: 11756860Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.Type: GrantFiled: July 25, 2019Date of Patent: September 12, 2023Assignee: Intel CorporationInventors: Shrenik Kothari, Chandra Mohan Jha, Weihua Tang, Robert Sankman, Xavier Brun, Pooya Tadayon
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Publication number: 20230271445Abstract: Reusable composite stencils for spray processes, particularly for spray processes used in the fabrication of integrated circuit devices, may be fabricated having a permanent core and at least one sacrificial material layer. Thus, in operation, when a predetermined amount of the sacrificial material layer has been ablated away by a material being sprayed in the spray process, the remaining sacrificial material layer may be removed and reapplied to its original thickness. Therefore, the permanent core, which is usually expensive and/or difficult to fabricate, may be repeatedly reused.Type: ApplicationFiled: February 25, 2022Publication date: August 31, 2023Applicant: Intel CorporationInventors: Feras Eid, Wenhao Li, Jiraporn Seangatith, Paul Diglio, Xavier Brun
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Publication number: 20230140685Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.Type: ApplicationFiled: December 27, 2022Publication date: May 4, 2023Inventors: Shrenik KOTHARI, Chandra Mohan JHA, Weihua TANG, Robert SANKMAN, Xavier BRUN, Pooya TADAYON
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Publication number: 20220357477Abstract: A method for automatically propagating a voltage along a marine seismic streamer, the method including detecting, at an ith concentrator of the streamer, a first voltage applied at a first high-voltage rail HV1; detecting, at the ith concentrator of the streamer, a second voltage applied at a second high-voltage rail HV2, the first and second high-voltage rails extend over the entire streamer; checking a predetermined condition at a first local controller of the ith concentrator; and closing a first switch SW1, which propagates the first high-voltage rail HV1, when the predetermined condition is satisfied.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Nicolas FRADIN, Xavier BRUN
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Patent number: 11480699Abstract: A marine seismic streamer includes plural concentrators, plural segments interposed with the plural concentrators so that a concentrator of the plural concentrators is sandwiched between two segments of the plural segments, a first high-voltage rail HV1 that extends along the plural concentrators and the plural segments, and a second high-voltage rail HV2 that extends along the plural concentrators and the plural segments. In each given concentrator i of the plural concentrators, there is a first switch SW1 placed along one of the first high-voltage rail HV1 and the second high-voltage rail HV2, a second switch SW2 placed between the first high-voltage rail HV1 and the second high-voltage rail HV2, a first local controller implemented in hardware, and a second local controller implemented in a combination of hardware and software, and having an operating system, the first local controller being separated from the second local controller.Type: GrantFiled: October 2, 2019Date of Patent: October 25, 2022Assignee: SERCELInventors: Nicolas Fradin, Xavier Brun
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Publication number: 20220165625Abstract: An integrated circuit package may be fabricated with a universal dummy device, instead of utilizing a dummy device that matches the bump layer of an electronic substrate of the integrated circuit package. In one embodiment, the universal dummy device may comprise a device substrate having an attachment surface and a metallization layer on the attachment surface, wherein the metallization layer is utilized to form a connection with the electronic substrate of the integrated circuit package. In a specific embodiment, the metallization layer may be a single structure extending across the entire attachment surface. In another embodiment, the metallization layer may be patterned to enable gap control between the universal dummy device and the electronic substrate.Type: ApplicationFiled: November 20, 2020Publication date: May 26, 2022Applicant: Intel CorporationInventors: Xavier Brun, Timothy Gosselin
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Publication number: 20210407884Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a backside metallization layer on the backside surface of the integrated circuit device, wherein the backside metallization layer comprises a bond layer on the backside surface of the integrated circuit device, a high thermal conductivity layer on the bond layer, and a cap layer on the high thermal conductivity layer. The bond layer may be a layered stack comprising an adhesion promotion layer on the backside of the integrated circuit device and at one least metal layer. The high thermal conductivity layer may be an additively deposited material having a thermal conductivity greater than silicon, such as copper, silver, aluminum, diamond, silicon carbide, boron nitride, aluminum nitride, and combinations thereof.Type: ApplicationFiled: June 25, 2020Publication date: December 30, 2021Applicant: Intel CorporationInventors: Feras Eid, Xavier Brun, Paul Diglio, Joe Walczyk, Sergio Antonio Chan Arguedas
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Publication number: 20210391244Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.Type: ApplicationFiled: June 10, 2020Publication date: December 16, 2021Inventors: Chandra Mohan JHA, Pooya TADAYON, Aastha UPPAL, Weihua TANG, Paul DIGLIO, Xavier BRUN
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Publication number: 20210249322Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Applicant: Intel CorporationInventors: Ziyin Lin, Vipul Mehta, Wei Li, Edvin Cetegen, Xavier Brun, Yang Guo, Soud Choudhury, Shan Zhong, Christopher Rumer, Nai-Yuan Liu, Ifeanyi Okafor, Hsin-Wei Wang
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Publication number: 20210103067Abstract: A marine seismic streamer includes plural concentrators, plural segments interposed with the plural concentrators so that a concentrator of the plural concentrators is sandwiched between two segments of the plural segments, a first high-voltage rail HV1 that extends along the plural concentrators and the plural segments, and a second high-voltage rail HV2 that extends along the plural concentrators and the plural segments. In each given concentrator i of the plural concentrators, there is a first switch SW1 placed along one of the first high-voltage rail HV1 and the second high-voltage rail HV2, a second switch SW2 placed between the first high-voltage rail HV1 and the second high-voltage rail HV2, a first local controller implemented in hardware, and a second local controller implemented in a combination of hardware and software, and having an operating system, the first local controller being separated from the second local controller.Type: ApplicationFiled: October 2, 2019Publication date: April 8, 2021Inventors: Nicolas FRADIN, Xavier BRUN