Patents by Inventor Xavier Brun
Xavier Brun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250210398Abstract: In some embodiments, a patternable TBDB for assembling 3D assemblies such as IC/optical assemblies are provided. A patternable TBDB adhesive may be formed using silicone based TBDB adhesives with incorporated photocatalysts to allow for patterning of the TBDB adhesive layer.Type: ApplicationFiled: December 20, 2023Publication date: June 26, 2025Inventors: Clay ARRINGTON, Bohan SHAN, Dingying XU, Jonas CROISSANT, Xavier BRUN, Jigneshkumar PATEL
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Publication number: 20250210392Abstract: Various aspects may provide a handling assembly. The handling assembly may include a body with a component-handling surface. The component-handling surface may include a first component-handling region configured to accommodate a first semiconductor component arrangement and a second component-handling region configured to accommodate a second semiconductor component arrangement. The handling assembly may further include an electrode arrangement disposed at the body in a manner so as to be capable of independently toggling each of the first component-handling region and the second component-handling region between an active state and an inactive state. In the active state the electrode arrangement may provide an electrostatic retention force over the component-handling region, configured to retain a corresponding semiconductor component arrangement on the component-handling region.Type: ApplicationFiled: December 22, 2023Publication date: June 26, 2025Inventors: Bhaskar Jyoti KRISHNATREYA, Michael J. BAKER, Feras EID, Wenhao LI, Veronica STRONG, Thomas SOUNART, Adel A. ELSHERBINI, Johanna M. SWAN, Kimin JUN, Yi SHI, Xavier BRUN, Shawna M. LIFF, Edison Chien-An CHEN
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Patent number: 12341080Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.Type: GrantFiled: March 21, 2024Date of Patent: June 24, 2025Assignee: Intel CorporationInventors: Shrenik Kothari, Chandra Mohan Jha, Weihua Tang, Robert Sankman, Xavier Brun, Pooya Tadayon
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Publication number: 20250112181Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die and a surface of a substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hydrophobic structures include non-vertical inward sloping sidewalls or similar features to contain a liquid droplet that is applied to the die or substrate hybrid bonding region. After the hybrid bonding regions are brought together, capillary forces cause the die to self-align, and a hybrid bond is formed by evaporating the liquid and subsequent anneal. IC structures including the IC die and portions of the substrate are segmented and assembled.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Feras Eid, Yi Shi, Kimin Jun, Adel Elsherbini, Thomas Sounart, Wenhao Li, Xavier Brun
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Publication number: 20250112177Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die backside surface and a surface of a structural substrate each include bonding regions surrounded by hydrophobic structures. A liquid droplet is applied to the die or structural substrate bonding region and the die is placed on the bonding region of the structural substrate. Capillary forces cause the die to self-align to the bonding region, and a bond is formed by evaporating the liquid and subsequent anneal. A hybrid bond is then formed between the opposing active surface of the die and a base substrate using wafer-to-wafer bonding. IC structures including the IC die and portions of the structural substrate and base substrate are segmented from the bonded wafers and assembled.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Feras Eid, Thomas Sounart, Yi Shi, Michael Baker, Adel Elsherbini, Kimin Jun, Xavier Brun, Wenhao Li
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Publication number: 20250006643Abstract: Microelectronic integrated circuit package structures include a package substrate with a first die over the package substrate, and a second die adjacent to the first die, such that first sides of the first die and the second die are on a thermal solution. A bridge structure is directly on a portion of each of second sides of the first and second dies, such that the second sides include integrated circuit contact structures. Bridge via structures couple the integrated circuit contact structures to the bridge structure.Type: ApplicationFiled: June 30, 2023Publication date: January 2, 2025Applicant: Intel CorporationInventors: Debendra Mallik, Ram Viswanath, Xavier Brun
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Publication number: 20240429199Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to self-align batch pick and place die bonding. Disclosed is an apparatus comprising a fluid dispensing assembly to dispense first amounts of water onto first hydrophilic regions of a first semiconductor wafer at a first point in time, the first hydrophilic regions having a first arrangement, and dispense second amounts of water onto second hydrophilic regions of a second semiconductor wafer at a second point in time, the second hydrophilic regions having a second arrangement, and a pick-and-place assembly to simultaneously position, at the first point in time, a first batch of dies corresponding to the first arrangement onto the first amounts of water dispensed on the first semiconductor wafer, and simultaneously position, at the second point in time, a second batch of dies corresponding to the second arrangement onto the second amounts of water dispensed on the second semiconductor wafer.Type: ApplicationFiled: June 23, 2023Publication date: December 26, 2024Inventors: Yi Shi, Bhaskar Jyoti Krishnatreya, Feras Eid, Xavier Brun, Johanna Swan
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Patent number: 12080620Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a backside metallization layer on the backside surface of the integrated circuit device, wherein the backside metallization layer comprises a bond layer on the backside surface of the integrated circuit device, a high thermal conductivity layer on the bond layer, and a cap layer on the high thermal conductivity layer. The bond layer may be a layered stack comprising an adhesion promotion layer on the backside of the integrated circuit device and at one least metal layer. The high thermal conductivity layer may be an additively deposited material having a thermal conductivity greater than silicon, such as copper, silver, aluminum, diamond, silicon carbide, boron nitride, aluminum nitride, and combinations thereof.Type: GrantFiled: June 25, 2020Date of Patent: September 3, 2024Assignee: Intel CorporationInventors: Feras Eid, Xavier Brun, Paul Diglio, Joe Walczyk, Sergio Antonio Chan Arguedas
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Patent number: 12066584Abstract: A method for automatically propagating a voltage along a marine seismic streamer, the method including detecting, at an ith concentrator of the streamer, a first voltage applied at a first high-voltage rail HV1; detecting, at the ith concentrator of the streamer, a second voltage applied at a second high-voltage rail HV2, the first and second high-voltage rails extend over the entire streamer; checking a predetermined condition at a first local controller of the ith concentrator; and closing a first switch SW1, which propagates the first high-voltage rail HV1, when the predetermined condition is satisfied.Type: GrantFiled: July 26, 2022Date of Patent: August 20, 2024Assignee: SERCELInventors: Nicolas Fradin, Xavier Brun
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Publication number: 20240234245Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.Type: ApplicationFiled: March 21, 2024Publication date: July 11, 2024Inventors: Shrenik KOTHARI, Chandra Mohan JHA, Weihua TANG, Robert SANKMAN, Xavier BRUN, Pooya TADAYON
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Patent number: 12021016Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.Type: GrantFiled: June 10, 2020Date of Patent: June 25, 2024Assignee: Intel CorporationInventors: Chandra Mohan Jha, Pooya Tadayon, Aastha Uppal, Weihua Tang, Paul Diglio, Xavier Brun
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Patent number: 12002727Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.Type: GrantFiled: February 11, 2020Date of Patent: June 4, 2024Assignee: Intel CorporationInventors: Ziyin Lin, Vipul Mehta, Wei Li, Edvin Cetegen, Xavier Brun, Yang Guo, Soud Choudhury, Shan Zhong, Christopher Rumer, Nai-Yuan Liu, Ifeanyi Okafor, Hsin-Wei Wang
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Publication number: 20240153837Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a die, and an array of pillars adjacent to the die. In an embodiment, the electronic package further comprises an underfill under the die, where an edge of the underfill is between an inner column of pillars in the array of pillars and an outer edge of the die, and where the edge of the underfill has a height that is less than a maximum height of the underfill.Type: ApplicationFiled: November 8, 2022Publication date: May 9, 2024Inventors: Ziyin LIN, Vipul MEHTA, Jonas CROISSANT, Jigneshkumar PATEL, Dingying XU, Gang DUAN, Aditya Sumanth YERRAMILLI, Suriyakala RAMALINGAM, Xavier BRUN
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Patent number: 11978689Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.Type: GrantFiled: December 27, 2022Date of Patent: May 7, 2024Assignee: Intel CorporationInventors: Shrenik Kothari, Chandra Mohan Jha, Weihua Tang, Robert Sankman, Xavier Brun, Pooya Tadayon
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Publication number: 20240113005Abstract: Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Jeremy Ecton, Aleksandar Aleksov, Hiroki Tanaka, Brandon Marin, Srinivas Pietambaram, Xavier Brun
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Publication number: 20240063089Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die and an inorganic dielectric material adjacent the integrated circuit dies and over the base die. The multichip composite device includes a dummy die, dummy vias, or integrated fluidic cooling channels laterally adjacent the integrated circuit dies to conduct heat from the base die.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel Elsherbini, Wenhao Li, Bhaskar Jyoti Krishnatreya, Debendra Mallik, Krishna Vasanth Valavala, Lei Jiang, Yoshihiro Tomita, Omkar Karhade, Haris Khan Niazi, Tushar Talukdar, Mohammad Enamul Kabir, Xavier Brun, Feras Eid
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Publication number: 20240063091Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel Elsherbini, Feras Eid, Scot Kellar, Yoshihiro Tomita, Rajiv Mongia, Kimin Jun, Shawna Liff, Wenhao Li, Johanna Swan, Bhaskar Jyoti Krishnatreya, Debendra Mallik, Krishna Vasanth Valavala, Lei Jiang, Xavier Brun, Mohammad Enamul Kabir, Haris Khan Niazi, Jiraporn Seangatith, Thomas Sounart
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Publication number: 20240063076Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die, a conformal thermal heat spreading layer on the top and sidewalls of the integrated circuit dies, and an inorganic dielectric material on a portion of the conformal thermal heat spreading layer, laterally adjacent the integrated circuit dies, and over the base die. The conformal thermal heat spreading layer includes a high thermal conductivity material to provide a thermal pathway for the integrated circuit dies during operation.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Mohammad Enamul Kabir, Bhaskar Jyoti Krishnatreya, Kimin Jun, Adel Elsherbini, Tushar Talukdar, Feras Eid, Debendra Mallik, Krishna Vasanth Valavala, Xavier Brun
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Publication number: 20240063071Abstract: Multi-die composite structures including a multi-layered inorganic dielectric gap fill material within a space between adjacent IC dies. A first layer of fill material with an inorganic composition may be deposited over IC dies with a high-rate deposition process, for example to at least partially fill a space between the IC dies. The first layer of fill material may then be partially removed to modify a sidewall slope of the first layer or otherwise reduce an aspect ratio of the space between the IC dies. Another layer of fill material may be deposited over the lower layer of fill material, for example with the same high-rate deposition process. This dep-etch-dep cycle may be repeated any number of times to backfill spaces between IC dies. The multi-layer fill material may then be globally planarized and the IC die package completed and/or assembled into a next-level of integration.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Jeffery Bielefeld, Adel Elsherbini, Bhaskar Jyoti Krishnatreya, Feras Eid, Gauri Auluck, Kimin Jun, Mohammad Enamul Kabir, Nagatoshi Tsunoda, Renata Camillo-Castillo, Tristan A. Tronic, Xavier Brun
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Publication number: 20240063142Abstract: Multi-die packages including IC die crack mitigation features. Prior to the bonding of IC dies to a host substrate, the IC dies may be shaped, for example with a corner radius or chamfer. After bonding the shaped IC dies, a fill comprising at least one inorganic material may be deposited over the IC dies, for example to backfill a space between adjacent IC dies. With the benefit of a greater IC die sidewall slope and/or smoother surface topology associated with the shaping process, occurrences of stress cracking within the fill and concomitant damage to the IC dies may be reduced. Prior to depositing a fill, a barrier layer may be deposited over the IC die to prevent cracks that might form in the fill material from propagating into the IC die.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel Elsherbini, Wenhao Li, Bhaskar Jyoti Krishnatreya, Tushar Talukdar, Botao Zhang, Yi Shi, Haris Khan Niazi, Feras Eid, Nagatoshi Tsunoda, Xavier Brun, Mohammad Enamul Kabir, Omkar Karhade, Shawna Liff, Jiraporn Seangatith