Abstract: Pedestals for semiconductors embedded in package substrates and related methods are disclosed. An example package substrate for an integrated circuit package disclosed herein includes core having a first surface, a second surface, and a cavity formed in the first surface, a semiconductor component disposed in the cavity, and a pedestal disposed in the cavity, the pedestal having a third surface coupled to the semiconductor component, and a fourth surface adjacent to the first surface, the pedestal dimensioned such that a first thickness of the pedestal and semiconductor is substantially equal to a second thickness of the core.

Abstract: In an illustrative embodiment, mechanical adhesive and a separate index-matching material are used as underfill between a photonic integrated circuit (PIC) die and an optical interposer. The index-matching material reduces coupling loss between waveguides of the PIC die and waveguides of the optical interposer, while the mechanical adhesive secures the optical interposer in place. The mechanical adhesive can be thermally cured, have a low coefficient of thermal expansion (CTE), have high viscosity, and have a relatively high optical transmission loss. The index-matching material can have low optical transmission loss, be UV cured, have a relatively high CTE, and have low viscosity. The combination of mechanical adhesive and index-matching material can improve ease of manufacture and yield. Additional features are disclosed, such as V-groove arrays in the optical interposer and the PIC die that have low stress and trenches and walls to control flow of the mechanical adhesive and/or index-matching material.

Abstract: An electronic device and associated methods are disclosed. Electronic devices are shown that include a semiconductor die and a patterned layer connected to a backside of the die. Electronic devices are shown that include a pattern of elements across a patterned layer that varies across the backside of a die. Electronic devices are further shown that include a compliant filler within elements in a patterned layer.

Abstract: Integrated circuit (IC) packages with pre-applied underfill in select areas, and methods of forming the same, are disclosed herein. In one example, an IC package includes a package substrate, a first IC die electrically coupled to the package substrate, a second IC die electrically coupled to the first IC die, and a thermoset adhesive that partially fills an area between the first IC die and the second IC die.

Abstract: Methods and apparatus for die shape modification bonding are disclosed. A disclosed apparatus to adjust a die for bonding to a target includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to determine a shape profile of the die, determine an adjustment of the shape profile with respect to the bonding of the die to the target, and cause at least one of (i) an actuator or (ii) a vacuum device of a placer that carries the die to adjust the shape profile based on the determined adjustment.

Abstract: Microelectronic integrated circuit package structures include a die having a dielectric die edge sidewall and a bulk silicon die edge sidewall, where the bulk silicon die edge sidewall is in substantial alignment with the dielectric die edge sidewall. The bulk silicon die edge sidewall has a plurality of scallop structures along a vertical distance of the bulk silicon die edge sidewall.

Abstract: Embodiments disclosed herein include multi-die modules. In an embodiment, the multi-die module comprises a first die and a second die coupled to the first die. In an embodiment, the second die comprises a keep out zone that at least partially overlaps the first die. The multi-die module may further comprise an underfill between the first die and the second die. In an embodiment, the underfill is entirely outside the keep out zone, and an edge of the underfill facing the keep out zone is non-vertical.

Abstract: Disclosed herein are microelectronics package architectures utilizing glass layers and methods of manufacturing the same. The microelectronics packages may include a silicon layer, dies, and a glass layer. The silicon layer may include vias. The dies may be in electrical communication with vias. The glass layer may include interconnects in electrical communication with the vias.

Abstract: Embodiments herein relate to systems, apparatuses, or processes creating a package that includes a die embedded in a molding, where a surface of the die is coplanar with a surface of the molding. During a stage of package manufacture, the die may have a finished side that may be coupled with a component of the package, and an unfinished side. During a subsequent stage of package manufacture, molding may be placed around the die, and then the molding and at least a portion of the die may be planarized, which may involve grinding and polishing. The planarization may reveal one or more TSV at the side of the die which is now finished and ready for electrical coupling with other components. As a result, a side of the molding at a side of the die to be coplanar. Other embodiments may be described and/or claimed.

Abstract: An integrated circuit (IC) device package substrate comprises a plurality of first interconnect features to couple to a first IC die, a plurality of second interconnect features to couple to a second IC die, and one or more barrier features on a surface of the substrate. The first interconnect features span a first length in a first direction on the surface of the substrate. The second interconnect features span a second length in the first direction on the surface of the substrate. The second interconnect features are between the first length of the first interconnect features and a first edge of the substrate. The one or more barrier features are between the first and second interconnect features, wherein the one or more barrier features span a third length in the first direction, the third length greater than at least one of the first or second lengths.

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an interface layer over the first dies, a backside metallization (BSM) layer directly on the interface layer, where the BSM layer includes first, second, and third conductive layer, and a heat spreader over the BSM layer. The first conductive layer includes a titanium material. The second conductive layer includes a nickel-vanadium material. The third conductive layer includes a gold material, a silver material, or a copper material. The copper material may include copper bumps. The semiconductor package may include a plurality of second dies on a package substrate. The substrate may be on the package substrate. The second dies may have top surfaces substantially coplanar to top surface of the first dies. The BSM and interface layers may be respectively over the first and second dies.

Abstract: Embodiments disclosed herein include chiplet modules and die modules. In an embodiment, a chiplet module comprises a first chiplet, where the first chiplet comprises a first active surface. In an embodiment the chiplet module further comprises a second chiplet, where the second chiplet comprises a second active surface. In an embodiment, the chiplet module further comprises a hybrid bonding interface between the first chiplet and the second chiplet, where the hybrid bonding interface electrically couples the first chiplet to the second chiplet.

Abstract: A semiconductor package includes a semiconductor subassembly disposed on a package substrate and including: a first layer including first dies, and an encapsulation material encapsulating the first dies; a second layer adjacent the first layer and including a substrate; a solid component disposed on the first layer; and an interface layer disposed between and mechanically bonding the solid component and the first layer. The interface layer provides a direct dielectric-to-dielectric bond including a first dielectric sublayer directly adjacent the first layer, and a second dielectric sublayer directly adjacent the first dielectric sublayer and including an amorphous material. Second dies may be disposed on the package substrate adjacent the semiconductor subassembly.

Abstract: Embodiments described herein include electronic packages. In an embodiment, an electronic package comprises a die and a through substrate via that passes through the die. In an embodiment, the through substrate via is coupled to a backside pad on the die. In an embodiment, a first layer is over the backside pad, where the first layer comprises a first dielectric material. In an embodiment, a second layer is over the first layer, where the second layer comprises a second dielectric material. In an embodiment, a via is through the first layer and the second layer.

Abstract: Technologies for optical coupling to photonic integrated circuit (PIC) dies are disclosed. In the illustrative embodiment, a lens assembly with one or more lenses is positioned to collimate light coming out of one or more waveguides in the PIC die. Part of the illustrative lens assembly extends above a top surface of the PIC die and is in contact with the PIC die. The top surface of the PIC die establishes the vertical positioning of the lens assembly. In the illustrative embodiment, the lens assembly is positioned at least partially inside a cavity defined within the PIC die, which allows the lens assembly to be integrated at the wafer level, before singulation into individual dies.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to multilevel dies, in particular to photonics integrated circuit dies with a thick portion and a thin portion, where the thick portion is placed within a cavity in a substrate and the thin portion serves as an overhang to physically couple with the substrate, to reduce a distance between electrical contacts on the thin portion of the die and electrical contacts on the substrate. Other embodiments may be described and/or claimed.

Abstract: A modular technique for die-level liquid cooling is described. In an example, an integrated circuit assembly includes a first silicon die comprising a device side and a backside opposite the device side. The integrated circuit assembly also includes a second silicon die comprising a plurality of fluidly accessible channels therein. A dielectric interface directly couples the second silicon die to a backside of the first silicon die.

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an interface layer over the first dies, a backside metallization (BSM) layer directly on the interface layer, where the BSM layer includes first, second, and third conductive layer, and a heat spreader over the BSM layer. The first conductive layer includes a titanium material. The second conductive layer includes a nickel-vanadium material. The third conductive layer includes a gold material, a silver material, or a copper material. The copper material may include copper bumps. The semiconductor package may include a plurality of second dies on a package substrate. The substrate may be on the package substrate. The second dies may have top surfaces substantially coplanar to top surface of the first dies. The BSM and interface layers may be respectively over the first and second dies.

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.