Patents by Inventor Xavier Hebras

Xavier Hebras has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8389380
    Abstract: A method for making a semiconductor on insulator (SeOI) type substrate that includes an integrated ground plane under the insulating layer wherein the substrate is intended to be used in making electronic components. This method includes implanting atoms or ions of a metal in at least one portion of a semiconducting receiver substrate, carrying out a heat treatment of the receiver substrate in order to obtain an integrated ground plane on or in at least one portion of that receiver substrate, transferring an active layer stemming from a semiconducting donor substrate onto the receiver substrate, with an insulating layer being inserted in between the donor and receiver substrates to obtain the substrate with an integrated ground plane.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: March 5, 2013
    Assignee: Soitec
    Inventor: Xavier Hebras
  • Patent number: 8212249
    Abstract: Various structures that include at least one thin layer of an amorphous material on a supporting substrate. One structure generally has a receiving substrate, a central crystalline layer and an amorphous layer, all of which may lack any end of range point defects. Another structure includes an intermediate substrate having an upper face, an upper portion and a lower portion, an amorphous layer that does not contain end of range point defects, and a first crystalline layer containing end of range point defects subjacent the amorphous layer and located in the lower portion; and a supporting substrate bonded to the upper face of the intermediate substrate. That structure can also contain a weakened zone or porous layer to facilitate removal of the first crystalline layer to provide the amorphous layer as an upper layer of the semiconductor structure.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: July 3, 2012
    Assignee: Soitec
    Inventor: Xavier Hebras
  • Publication number: 20100207236
    Abstract: A method for making a semiconductor on insulator (SeOI) type substrate that includes an integrated ground plane under the insulating layer wherein the substrate is intended to be used in making electronic components. This method includes implanting atoms or ions of a metal in at least one portion of a semiconducting receiver substrate, carrying out a heat treatment of the receiver substrate in order to obtain an integrated ground plane on or in at least one portion of that receiver substrate, transferring an active layer stemming from a semiconducting donor substrate onto the receiver substrate, with an insulating layer being inserted in between the donor and receiver substrates to obtain the substrate with an integrated ground plane.
    Type: Application
    Filed: October 10, 2008
    Publication date: August 19, 2010
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventor: Xavier Hebras
  • Publication number: 20100044706
    Abstract: Various structures that include at least one thin layer of an amorphous material on a supporting substrate. One structure generally has a receiving substrate, a central crystalline layer and an amorphous layer, all of which may lack any end of range point defects. Another structure includes an intermediate substrate having an upper face, an upper portion and a lower portion, an amorphous layer that does not contain end of range point defects, and a first crystalline layer containing end of range point defects subjacent the amorphous layer and located in the lower portion; and a supporting substrate bonded to the upper face of the intermediate substrate. That structure can also contain a weakened zone or porous layer to facilitate removal of the first crystalline layer to provide the amorphous layer as an upper layer of the semiconductor structure.
    Type: Application
    Filed: August 4, 2009
    Publication date: February 25, 2010
    Inventor: Xavier Hebras
  • Patent number: 7632739
    Abstract: A process for fabricating a hybrid substrate that has a defect trapping zone. The process includes the steps of forming or depositing a first insulator layer on a first substrate of semiconductor material; increasing roughness of the first insulator layer surface; depositing a second insulator layer on the roughened surface of the first insulator to form a trapping zone between the layers; bonding a second substrate onto the second insulator layer by molecular adhesion; and transferring an active layer formed by the implantation of atomic species into one of the substrates. The trapping zone is able to retain gaseous species present at the various interfaces of the hybrid substrate to limit the formation of defects on the surface of the active layer that is transferred.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: December 15, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technolgies
    Inventor: Xavier Hebras
  • Patent number: 7585749
    Abstract: A method for making a structure which may have at least one layer on a supporting substrate. The method includes at least the steps for forming from the supporting substrate an intermediate structure which may have an amorphous layer, a first crystalline layer containing point defects and, a second crystalline layer located immediately underneath the amorphous layer and in the lower portion of the intermediate structure. The method may also include bonding a receiving substrate on the upper face of the intermediate structure and removing the layer of the intermediate structure in which point defects have formed so that amorphous layer forms the upper layer of the intermediate structure. A structure made by such a method may comprise at least one thin layer of an amorphous material on a supporting substrate. The structure may comprise a receiving substrate, a central crystalline layer and an amorphous layer, all of which may lack any EOR type point defect.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: September 8, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Xavier Hebras
  • Patent number: 7485551
    Abstract: The present invention relates to a method of fabricating a semiconductor-on-insulator-type heterostructure that includes at least one insulating layer interposed between a receiver substrate of semiconductor material and an active layer derived from a donor substrate of semiconductor material. The method includes the steps of bonding and active layer transfer. Prior to bonding, an atomic species which is identical or isoelectric with the insulating layer material is implanted in the insulating layer. The implantation forms a trapping layer, which can retain gaseous species present in the various interfaces of the heterostructure, thereby limiting formation of defects on the surface of the active layer.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: February 3, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Xavier Hebras
  • Publication number: 20080171443
    Abstract: A process for fabricating a hybrid substrate that has a defect trapping zone. The process includes the steps of forming or depositing a first insulator layer on a first substrate of semiconductor material; increasing roughness of the first insulator layer surface; depositing a second insulator layer on the roughened surface of the first insulator to form a trapping zone between the layers; bonding a second substrate onto the second insulator layer by molecular adhesion; and transferring an active layer formed by the implantation of atomic species into one of the substrates. The trapping zone is able to retain gaseous species present at the various interfaces of the hybrid substrate to limit the formation of defects on the surface of the active layer that is transferred.
    Type: Application
    Filed: August 9, 2007
    Publication date: July 17, 2008
    Inventor: Xavier HEBRAS
  • Publication number: 20080064182
    Abstract: The invention concerns a method for transferring a thin layer from a donor wafer onto a receiving wafer by implanting at least one atomic species into the donor wafer to form a weakened zone therein, with the weakened zone being including microcavities or platelets therein, and the thin layer being defined between the weakened zone and a surface of the donor wafer; molecular bonding of the surface of the donor wafer onto a surface of the receiving wafer; splitting the thin layer at the zone of weakness by heating to a high temperature to transfer the thin layer to the receiving substrate; and treating the donor wafer to block or limit the formation of microcavities or platelets by trapping the atoms of at least one of the implanted atomic species at least until a certain release temperature is reached during the splitting. This method enables bonding energy to be reinforced adjacent the layer to be transferred and hence limits defects in the resulting heterostructure.
    Type: Application
    Filed: January 10, 2007
    Publication date: March 13, 2008
    Inventor: Xavier Hebras
  • Publication number: 20070210307
    Abstract: A method for making a structure which may have at least one layer on a supporting substrate. The method includes at least the steps for forming from the supporting substrate an intermediate structure which may have an amorphous layer, a first crystalline layer containing point defects and, a second crystalline layer located immediately underneath the amorphous layer and in the lower portion of the intermediate structure. The method may also include bonding a receiving substrate on the upper face of the intermediate structure and removing the layer of the intermediate structure in which point defects have formed so that amorphous layer forms the upper layer of the intermediate structure. A structure made by such a method may comprise at least one thin layer of an amorphous material on a supporting substrate. The structure may comprise a receiving substrate, a central crystalline layer and an amorphous layer, all of which may lack any EOR type point defect.
    Type: Application
    Filed: August 14, 2006
    Publication date: September 13, 2007
    Inventor: Xavier Hebras
  • Publication number: 20070054466
    Abstract: The present invention relates to a method of fabricating a semiconductor-on-insulator-type heterostructure that includes at least one insulating layer interposed between a receiver substrate of semiconductor material and an active layer derived from a donor substrate of semiconductor material. The method includes the steps of bonding and active layer transfer. Prior to bonding, an atomic species which is identical or isoelectric with the insulating layer material is implanted in the insulating layer. The implantation forms a trapping layer, which can retain gaseous species present in the various interfaces of the heterostructure, thereby limiting formation of defects on the surface of the active layer.
    Type: Application
    Filed: January 5, 2006
    Publication date: March 8, 2007
    Inventor: Xavier Hebras
  • Publication number: 20070026650
    Abstract: A method of fabricating a heterostructure comprising at least a first layer of semi-conductor material such as, for example, a silicon-germanium (SiGe) layer on a second layer or a substrate of another material. The material of the second layer may differ from that of the first layer. To prevent elements of the semiconductor material of the first layer from diffusing into the first layer as well as the adjacent layers by a vacancy mechanism, the first layer may be enriched with interstitial defects to limit vacancy diffusion of elements of the first layer.
    Type: Application
    Filed: September 13, 2006
    Publication date: February 1, 2007
    Inventor: Xavier Hebras