Patents by Inventor Xavier Hours

Xavier Hours has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11416378
    Abstract: An integrated circuit device is disclosed. The device includes a circuit configured to perform a function, a fault management component, at least one user register, an analog test bus component, a built-in self-test component, a safety monitor component, and gating logic. Additionally, the circuit is separated from the fault management component, the at least one user register, the analog test bus component, the built-in self-test component, the safety monitor, and the gating logic.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: August 16, 2022
    Assignee: NXP B.V.
    Inventors: Jan-Peter Schat, Xavier Hours, Andres Barrilado Gonzalez
  • Publication number: 20200073786
    Abstract: An integrated circuit device is disclosed. The device includes a circuit configured to perform a function, a fault management component, at least one user register, an analog test bus component, a built-in self-test component, a safety monitor component, and gating logic. Additionally, the circuit is separated from the fault management component, the at least one user register, the analog test bus component, the built-in self-test component, the safety monitor, and the gating logic.
    Type: Application
    Filed: May 13, 2019
    Publication date: March 5, 2020
    Inventors: Jan-Peter Schat, Xavier Hours, Andres Barrilado Gonzalez
  • Patent number: 10121373
    Abstract: An apparatus for reporting traffic information comprises a mobile device. The mobile device comprises one or more sensor for monitoring an environmental condition, a memory for storing one or more template. A signal processing module is present for comparing the monitored environmental condition with a selected one of the one or more template indicative of a type of environmental condition. The module generates a event notification message when the monitored environmental condition matches the selected template, the event notification message including information of the type of environmental condition. A transmitter is arranged to transmit the event notification message to a remote station.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: November 6, 2018
    Assignee: NXP USA, Inc.
    Inventors: Rainer Makowitz, Frodo Ferro, Xavier Hours, Christophe Oger
  • Patent number: 10041993
    Abstract: The use of a netlist or other database containing topological information of an electrical circuit comprising a multiplicity of components which are to undergo safe operating area (SOA) checking, permits a relationship between recorded SOA errors to be established. Knowing how such errors may be interdependent can assist designers in deciding which errors should be rectified first. The relationship between the recorded errors relating to two connected components may be modified by a confidence factor based on elapsed time between the occurrence of the two recorded errors.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: August 7, 2018
    Assignee: NXP USA, Inc.
    Inventors: Xavier Hours, Aldric L'Hernault, Christophe Oger, Mehul Shroff
  • Patent number: 9846758
    Abstract: A method of designing an integrated circuit is described. The integrated circuit comprises a plurality of circuit components, including one or more functional components and one or more tile shapes. A pcell instance may be defined to specify a functional component along with one or more tile shapes. The tile shapes are thus associated with the functional component. A netlist may be arranged to specify interconnections between the functional components of the integrated circuit as well as electrical interactions between the tile shapes and functional components. A computer program product for carrying out the method is also described.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: December 19, 2017
    Assignee: NXP USA, Inc.
    Inventors: Xavier Hours, David M. Grochowski, Bernd E. Kastenmeier, Karl Wimmer
  • Patent number: 9712054
    Abstract: A design verification system simulates operation of an electronic device to identify one or more power characteristic vs. temperature (PC-T) curves for the electronic device. Each of the one or more PC-T curves indicates, for a particular reliability characteristic limit, a range of power characteristic values over a corresponding range of temperatures that are not expected to result in the reliability characteristic limit being exceeded. Based on the one or more PC-T curves, the design verification system sets a range of power characteristic limits, over a corresponding range of temperatures, for the electronic device. During operation, the electronic device employs a temperature sensor to measure an ambient or device temperature, and sets its power characteristic (voltage or current) according to the measured temperature and the power characteristic limits.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: July 18, 2017
    Assignee: NXP USA, INC.
    Inventors: Mehul D. Shroff, Xavier Hours
  • Patent number: 9443041
    Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of the device using a device design, a device model and a simulation scenario; and one or more violation monitor for each violation rule. At least one of the violation monitors comprises a violation information detector and a threshold controller. The violation information detector is arranged to detect one or more violations of the respective violation rule of the one or more violation rules during the executing the simulation of the device and, for each violation, determine information representing the respective violation, wherein the detecting the one or more violations comprises comparing a simulated parameter against a threshold.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 13, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mehul Shroff, Peter Abramowitz, Xavier Hours
  • Patent number: 9424379
    Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. Each violation monitor comprises a violation information detector for detecting one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determining information representing the respective violation; a violation score unit for calculating, for each violation of the respective violation rule, a violation score in dependence on the information representing the violation and on a violation rule-specific scheme, and a rule score unit for determining, for the respective violation rule, a rule score from the violation scores of the one or more violations during the simulation.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: August 23, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xavier Hours, Pascal Caunegre, Christophe Oger, Mehul Shroff
  • Publication number: 20160223608
    Abstract: The use of a netlist or other database containing topological information of an electrical circuit comprising a multiplicity of components which are to undergo safe operating area (SOA) checking, permits a relationship between recorded SOA errors to be established. Knowing how such errors may be interdependent can assist designers in deciding which errors should be rectified first. The relationship between the recorded errors relating to two connected components may be modified by a confidence factor based on elapsed time between the occurrence of the two recorded errors.
    Type: Application
    Filed: September 5, 2013
    Publication date: August 4, 2016
    Inventors: Xavier HOURS, Aldric L'HERNAULT, Christophe OGER, Mehul SHROFF
  • Patent number: 9378325
    Abstract: A method of performing layout verification for an integrated circuit (IC) layout is described. The method comprises receiving layout information for the IC layout, identifying at least one IC component within the IC layout, extracting localized layout information for the at least one IC component from the received layout information, defining the localized layout information for the at least one IC component within at least one component instance parameter therefor, and performing at least one layout verification check for the at least one component based at least partly on the at least one component instance parameter.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: June 28, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xavier Hours, Shitiz Arora, Robert Scott Ruth
  • Publication number: 20160132628
    Abstract: A method of designing an integrated circuit is described. The integrated circuit comprises a plurality of circuit components, including one or more functional components and one or more tile shapes. A pcell instance may be defined to specify a functional component along with one or more tile shapes. The tile shapes are thus associated with the functional component. A netlist may be arranged to specify interconnections between the functional components of the integrated circuit as well as electrical interactions between the tile shapes and functional components. A computer program product for carrying out the method is also described.
    Type: Application
    Filed: July 23, 2013
    Publication date: May 12, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Xavier HOURS, David M. GROCHOWSKI, Bernd E. KASTENMEIER, Karl WIMMER
  • Publication number: 20150363533
    Abstract: A design verification system simulates operation of an electronic device to identify one or more power characteristic vs. temperature (PC-T) curves for the electronic device. Each of the one or more PC-T curves indicates, for a particular reliability characteristic limit, a range of power characteristic values over a corresponding range of temperatures that are not expected to result in the reliability characteristic limit being exceeded. Based on the one or more PC-T curves, the design verification system sets a range of power characteristic limits, over a corresponding range of temperatures, for the electronic device. During operation, the electronic device employs a temperature sensor to measure an ambient or device temperature, and sets its power characteristic (voltage or current) according to the measured temperature and the power characteristic limits.
    Type: Application
    Filed: October 28, 2014
    Publication date: December 17, 2015
    Inventors: Mehul D. Shroff, Xavier Hours
  • Publication number: 20150269841
    Abstract: An apparatus for reporting traffic information comprises a mobile device. The mobile device comprises one or more sensor for monitoring an environmental condition, a memory for storing one or more template. A signal processing module is present for comparing the monitored environmental condition with a selected one of the one or more template indicative of a type of environmental condition. The module generates a event notification message when the monitored environmental condition matches the selected template, the event notification message including information of the type of environmental condition. A transmitter is arranged to transmit the event notification message to a remote station.
    Type: Application
    Filed: October 15, 2012
    Publication date: September 24, 2015
    Inventors: Rainer Makowitz, Frodo Ferro, Xavier Hours, Christophe Oger
  • Publication number: 20150234961
    Abstract: A method for integrated circuit reliability aging simulation includes dividing a target time period into N stages including a first stage and a second stage; obtaining first parameter values of a reliability model for the first stage; performing a first simulation on the circuit based on the reliability model and the first parameter values to obtain first aging results; obtaining second parameter values of the reliability model for the second stage; and performing a second simulation on the circuit based on the reliability model and the second parameter values to obtain second aging results.
    Type: Application
    Filed: December 2, 2014
    Publication date: August 20, 2015
    Inventors: Zhichen Zhang, Xavier Hours, Mehul D. Shroff, Chuanzheng Wang, Qilin Zhang
  • Publication number: 20150143308
    Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. At least one of the violation monitors comprises a violation information detector and a threshold controller. The violation information detector is arranged to detect one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determine information representing the respective violation, wherein detecting the one or more violations comprises comparing a simulated parameter against a threshold. The threshold controller is arranged to determine the threshold for the respective violation rule in dependence on a temporal characteristic of the associated violation.
    Type: Application
    Filed: September 13, 2012
    Publication date: May 21, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Mehul Shroff, Peter Abramowitz, Xavier Hours
  • Publication number: 20150121325
    Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. Each violation monitor comprises a violation information detector for detecting one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determining information representing the respective violation; a violation score unit for calculating, for each violation of the respective violation rule, a violation score in dependence on the information representing the violation and on a violation rule-specific scheme, and a rule score unit for determining, for the respective violation rule, a rule score from the violation scores of the one or more violations during the simulation.
    Type: Application
    Filed: May 31, 2012
    Publication date: April 30, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Xavier Hours, Pascal Caunegre, Christophe Oger, Mehul Shroff
  • Publication number: 20140380258
    Abstract: A method of performing layout verification for an integrated circuit (IC) layout is described. The method comprises receiving layout information for the IC layout, identifying at least one IC component within the IC layout, extracting localised layout information for the at least one IC component from the received layout information, defining the localised layout information for the at least one IC component within at least one component instance parameter therefor, and performing at least one layout verification check for the at least one component based at least partly on the at least one component instance parameter.
    Type: Application
    Filed: February 23, 2012
    Publication date: December 25, 2014
    Applicant: Freescale Semiconductor, Inc
    Inventors: Xavier Hours, Shitiz Arora, Robert Scott Ruth