Abstract: The systems and methods disclosed relate to a processor comprising a processing unit and a debugging that which can be connected to an external emulator for debugging a program executed by the processor, the debugging interface including internal resources at least partially accessible to the external emulator. According to one embodiment, the debugging interface includes a selecting circuit for selecting an internal resource of the debugging interface, according to a reference supplied by the processing unit, and an access circuit that transfers a datum between the resource selected and a data field accessible by the processing unit.

Abstract: A method for the transmission of digital messages by the output terminals of a monitoring circuit which is integrated into a microprocessor, the digital messages being representative of first specific events which are dependent on the execution of a series of instructions by the microprocessor.

Abstract: The systems and methods disclosed relate to a processor comprising a processing unit and a debugging interface which can be connected to an external emulator for debugging a program executed by the processor, the debugging interface comprising internal resources at least partially accessible to the external emulator. According to one embodiment, the debugging interface comprises a selecting circuit for selecting an internal resource of the debugging interface, according to a reference supplied by the processing unit, and access means for transferring a datum between the resource selected and a data field accessible by the processing unit.

Abstract: The invention concerns a monitoring device (18) integrated to a microprocessor chip (12) executing a series of instructions comprising: device (26) for producing simultaneously several types of monitoring messages of the microprocessor, a buffer (28) divided into several blocks (A, B, C, D, E) each of which is designed to store only messages of one of the types capable of being produced simultaneously, the size of each block depending on the maximum frequency at which the messages can be stored, and device (26) for, each time one or more messages are simultaneously stored in the blocks (A, B, C, D, E) of the buffer (28), storing in a predetermined block (F) of the buffer a coded value representing said block(s) of the buffer.

Abstract: The invention relates to a method for the transmission of digital messages by means of the output terminals (22) of a monitoring circuit (18) which is integrated into a microprocessor (12), said digital messages being representative of first specific events which are dependent on the execution of a series of instructions by the microprocessor.

Abstract: The invention concerns a monitoring device (18) integrated to a microprocessor chip (12) executing a series of instructions comprising: means (26) for producing simultaneously several types of monitoring messages of the microprocessor, a buffer (28) divided into several blocks (A, B, C, D, E) each of which is designed to store only messages of one of the types capable of being produced simultaneously, the size of each block depending on the maximum frequency at which the messages can be stored, and means (26) for, each time one or more messages are simultaneously stored in the blocks (A, B, C D, E) of the buffer (28), storing in a predetermined block (F) of the buffer a coded value representing said block(s) of the buffer

Abstract: The invention relates to a method for the transmission of digital messages by a monitoring circuit (18) which is integrated into a microprocessor (12), said method being performed during the execution of a series of instructions by the microprocessor. Moreover, at least one of said digital messages represents the detection of a jump in the execution of the series of instructions from a source instruction to a destination instruction. The inventive method consists in determining whether or not the jump is associated with a jump instruction from the series of instructions for which the address of the jump destination instruction is explicitly indicated in the instruction. If the answer is in the affirmative, a first value is allocated to a first set of bits or, if the answer is in the negative, a second value is allocated to the first set of bits.

Abstract: The component essentially includes three subtracter operators (ST1-ST3) connected between two multiplexers (MUX1, MUX2), associated with a shifter (DEC) for shifting the dividend and a concatenator means (MCT) for delivering the successive partial dividends from the contents of an output flip-flop (B3) and from the successive shifted words (S). The final-result word is stored in a shift register (RG). The component may be applied to image processing.