Abstract: There is provided a method and server for estimating an uncertainty parameter of a sequence of computer-implemented models comprising at least one machine learning algorithm (MLA). A set of labelled digital documents is received, which is to be processed by the sequence of models. For a given model of the sequence of models, at least one of a respective set of input features, a respective set of model-specific features and a respective set of output features are received. The set of predictions output by the sequence of models is received. A second MLA is trained to estimate uncertainty of the sequence of models based on the set of labelled digital documents, and the at least one of the respective set of input features, the respective set of model-specific features, the respective set of output features, and the set of predictions.

Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

Abstract: A solid state drive (SSD) includes dynamic random access memory (DRAM), flash memory, and a solid state drive (SSD) controller. The solid state drive (SSD) also includes a peripheral component interconnect express (PCIe) bus to connect the SSD to a computing device such that a central processing unit (CPU) of the computing device exclusively reads data from, and writes data to, the DRAM. The SSD controller writes data to the flash memory from the DRAM independently of received commands from the computing device.

Abstract: There is provided a method and server for estimating an uncertainty parameter of a sequence of computer-implemented models comprising at least one machine learning algorithm (MLA). A set of labelled digital documents is received, which is to be processed by the sequence of models. For a given model of the sequence of models, at least one of a respective set of input features, a respective set of model-specific features and a respective set of output features are received. The set of predictions output by the sequence of models is received. A second MLA is trained to estimate uncertainty of the sequence of models based on the set of labelled digital documents, and the at least one of the respective set of input features, the respective set of model-specific features, the respective set of output features, and the set of predictions.

Abstract: A solid state drive (SSD) includes dynamic random access memory (DRAM), flash memory, and a solid state drive (SSD) controller. The solid state drive (SSD) also includes a peripheral component interconnect express (PCIe) bus to connect the SSD to a computing device such that a central processing unit (CPU) of the computing device exclusively reads data from, and writes data to, the DRAM. The SSD controller writes data to the flash memory from the DRAM independently of received commands from the computing device.

Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

Abstract: A solid state drive (SSD) includes dynamic random access memory (DRAM), flash memory, and a solid state drive (SSD) controller. The solid state drive (SSD) also includes a peripheral component interconnect express (PCIe) bus to connect the SSD to a computing device such that a central processing unit (CPU) of the computing device exclusively reads data from, and writes data to, the DRAM. The SSD controller writes data to the flash memory from the DRAM independently of received commands from the computing device.

Abstract: Systems and methods are disclosed for providing communication between processor-based devices. The system includes at least one processor-readable medium communicatively coupled to at least one processor and which stores processor-executable instructions that, when executed by the at least one processor, cause the at least one processor to: identify a first textual message generated at a first processor-based device that is designated for visual presentation via a second processor-based device, the first textual message including a plurality of alphanumeric characters; perform a classification on the first textual message that converts the first textual message into one or more graphic or pictorial symbols; and cause a presentation of the one or more graphic or pictorial symbols in lieu of, and without presentation of, the first textual message using the second processor-based device.

Abstract: Systems and methods are disclosed for providing communication between processor-based devices. The system includes at least one processor-readable medium communicatively coupled to at least one processor and which stores processor-executable instructions that, when executed by the at least one processor, cause the at least one processor to: identify a first textual message generated at a first processor-based device that is designated for visual presentation via a second processor-based device, the first textual message including a plurality of alphanumeric characters; perform a classification on the first textual message that converts the first textual message into one or more graphic or pictorial symbols; and cause a presentation of the one or more graphic or pictorial symbols in lieu of, and without presentation of, the first textual message using the second processor-based device.

Abstract: Systems and methods are disclosed for providing communication between processor-based devices. The system includes at least one processor-readable medium communicatively coupled to at least one processor and which stores processor-executable instructions that, when executed by the at least one processor, cause the at least one processor to: identify a first textual message generated at a first processor-based device that is designated for visual presentation via a second processor-based device, the first textual message including a plurality of alphanumeric characters; perform a classification on the first textual message that converts the first textual message into one or more graphic or pictorial symbols; and cause a presentation of the one or more graphic or pictorial symbols in lieu of, and without presentation of, the first textual message using the second processor-based device.

Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

Abstract: A one-dimensional input system is provided. The input system comprises a plurality of characters arranged on a single dimension. User input along the dimension is continuously disambiguated. The characters may be arranged based on factors including motor efficiency, optimization of disambiguation and learnability. A touchscreen interface of the one-dimensional input system is provided. A gesture-based interface of the one-dimensional input system is also provided.

Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.