Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.

Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.

Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.

Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.

Abstract: Systems-on-chip are designed with different IPs that use different data protection schemes. Modules are used between the IPs, and the modules convert between protection schemes. Protection schemes can be per-byte, word, packet, flit, or burst. Conversion can involve splitting, merging, encapsulation, conversion, and generation of redundant information. Encoding of redundancy according to protection schemes can occur directly at an IP interface or within an interconnect, such as within a packet-based NoC. Designs include SoCs, hardware description language code describing functions within SoCs, and non-transient computer readable media that store such source code.

Abstract: A system and method for detecting writes of data to errant locations in storage arrays. Address information and information redundant with address information is encoded and stored in proximity with data. Upon reading the stored data, the corresponding address information is decoded and compared to the address of the intended read. A mismatch indicates a possible write to an errant location.

Abstract: A system and method of defining the topology of a network-on-chip. The IP sockets and their data transfer connectivity are defined. The location of each IP socket is defined. A number of switches are defined so that there is at least one switch within a distance from each IP socket, the distance being less than that over which a signal propagates within one clock cycle period. The switches are coupled by links. Links may comprise pipeline stages, storage buffers, and are characterized by a data width.

Abstract: A system and method for detecting writes of data to errant locations in storage arrays. Address information and information redundant with address information is encoded and stored in proximity with data. Upon reading the stored data, the corresponding address information is decoded and compared to the address of the intended read. A mismatch indicates a possible write to an errant location.

Abstract: Systems-on-chip are designed with different IPs that use different data protection schemes. Modules are used between the IPs, and the modules convert between protection schemes. Protection schemes can be per-byte, word, packet, flit, or burst. Conversion can involve splitting, merging, encapsulation, conversion, and generation of redundant information. Encoding of redundancy according to protection schemes can occur directly at an IP interface or within an interconnect, such as within a packet-based NoC. Designs include SoCs, hardware description language code describing functions within SoCs, and non-transient computer readable media that store such source code.

Abstract: A system and method of defining the topology of a network-on-chip. The IP sockets and their data transfer connectivity are defined. The location of each IP socket is defined. A number of switches are defined so that there is at least one switch within a distance from each IP socket, the distance being less than that over which a signal propagates within one clock cycle period. The switches are coupled by links. Links may comprise pipeline stages, storage buffers, and are characterized by a data width.

Abstract: A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way.

Abstract: A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way.

Abstract: A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way.

Abstract: A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way.