Patents by Inventor Xeujun Yuan

Xeujun Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7109757
    Abstract: One embodiment of the present invention provides a circuit which blocks a keeper from interfering with a dynamic node during an evaluation phase for a dynamic wide-NOR structure. The circuit contains a precharge device which is coupled to the dynamic node. The precharge device precharges the dynamic node during a precharge phase. The circuit also contains a plurality of parallel pull-down transistors which are coupled to the dynamic node. The pull-down transistors conditionally discharge the dynamic node during the evaluate phase. The keeper sustains a precharged value on the dynamic node, thereby preventing a false evaluation caused by a leakage current through the parallel pull-down transistors. In addition, the circuit contains a feedback gating device which is coupled between the keeper and the dynamic node. During the evaluation phase, the feedback gating device blocks the keeper, so that the parallel pull-down transistors can discharge the dynamic node without interference from the keeper.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: September 19, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Xeujun Yuan, Ye Xiong, Peter F. Lai
  • Publication number: 20060103430
    Abstract: One embodiment of the present invention provides a circuit which blocks a keeper from interfering with a dynamic node during an evaluation phase for a dynamic wide-NOR structure. The circuit contains a precharge device which is coupled to the dynamic node. The precharge device precharges the dynamic node during a precharge phase. The circuit also contains a plurality of parallel pull-down transistors which are coupled to the dynamic node. The pull-down transistors conditionally discharge the dynamic node during the evaluate phase. The keeper sustains a precharged value on the dynamic node, thereby preventing a false evaluation caused by a leakage current through the parallel pull-down transistors. In addition, the circuit contains a feedback gating device which is coupled between the keeper and the dynamic node. During the evaluation phase, the feedback gating device blocks the keeper, so that the parallel pull-down transistors can discharge the dynamic node without interference from the keeper.
    Type: Application
    Filed: November 15, 2004
    Publication date: May 18, 2006
    Inventors: Xeujun Yuan, Ye Xiong, Peter Lai