Patents by Inventor Xi CEN

Xi CEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260164744
    Abstract: A method of forming a metal silicide layer in a semiconductor structure includes performing a silicide deposition process in a processing chamber, in which a metal silicide layer is formed on silicon surfaces within an opening formed in a semiconductor structure, inner surfaces of the opening comprising the silicon surfaces, wherein the silicide deposition process including performing a pre-dose purging process, in which the processing chamber is evacuated at a first pressure, performing a dose process, in which a metal-containing precursor is flowed in the processing chamber at a second pressure that is higher than the first pressure, performing a post-dose purge process, in which the processing chamber is purged at a third pressure that is lower than the second pressure, and performing an anneal process at a fourth pressure that is higher than the second pressure.
    Type: Application
    Filed: December 10, 2024
    Publication date: June 11, 2026
    Inventors: Ying-Bing JIANG, Yuxin WANG, Joung Joo LEE, Avgerinos V. GELATOS, Yuan-Chung WEN, Tom H. YU, Yao XU, Cheng CHENG, Xi CEN, Kai WU
  • Patent number: 12652980
    Abstract: A method of filling a feature in a semiconductor structure with metal includes depositing a metal cap layer on a bottom surface of a feature formed within a dielectric layer and top surfaces of the dielectric layer, partially filling the feature from the bottom surface with a flowable polymer layer, performing a metal pullback process to remove the metal cap layer on the top surfaces of the dielectric layer selectively to the dielectric layer, wherein the metal pullback process includes a first etch process including a chemical etch process using molybdenum hexafluoride (MoF6) to remove the metal cap layer selectively to the dielectric layer, and a second etch process to remove residues on etched surfaces of the dielectric layer, removing the flowable polymer layer, pre-cleaning a surface of the metal cap layer, and filling the feature from the surface of the metal cap layer with metal fill material.
    Type: Grant
    Filed: May 3, 2023
    Date of Patent: June 9, 2026
    Assignee: Applied Materials, Inc.
    Inventors: Qihao Zhu, Chi Hong Ching, Liqi Wu, Tsungjui Liu, Gaurav Thareja, Xinke Wang, Feng Q. Liu, Xi Cen, Kai Wu, Yixiong Yang, Yuanhung Liu, Jiang Lu, Rongjun Wang, Xianmin Tang
  • Publication number: 20260130137
    Abstract: A method of forming and post-treating a metal silicide layer in a semiconductor structure includes performing a silicide deposition process, in which a metal silicide layer is deposited on a substrate, performing a chemical vapor deposition (CVD) soak process in which the metal silicide layer is exposed to a nitrogen (N)-containing liquid precursor, forming a metal silicide nitride layer, and performing a cap deposition process, in which a cap layer is deposited on the metal silicide nitride layer.
    Type: Application
    Filed: November 1, 2024
    Publication date: May 7, 2026
    Inventors: Xi CEN, Ying-Bing JIANG, Yuxin WANG, Yao XU, Avgerinos V. GELATOS, Joung Joo LEE, Kai WU, Cheng CHENG
  • Publication number: 20260052960
    Abstract: Methods used in electronic device manufacturing and, more particularly, to methods used for forming metal containing interconnect features in a semiconductor device. In one aspect, a method of forming a boron nitride layer on a metal surface is provided. The method includes exposing a surface of a metal layer to a nitrogen-containing plasma to form a metal nitride layer on the surface. The method further includes performing a chemical vapor deposition (CVD) soak process in which the metal nitride layer is exposed to a boron (B)-containing precursor gas, form a boron nitride monolayer.
    Type: Application
    Filed: January 30, 2025
    Publication date: February 19, 2026
    Inventors: Yao XU, Xi CEN, Kai WU, Cheng CHENG, Rongjun WANG, Xianmin TANG
  • Publication number: 20250300015
    Abstract: A method of filling a via having a necking point includes executing one or more cycles, each cycle including performing a pre-clean process to remove metal oxides from an exposed surface of a metal layer at a bottom of the via and recover inner surfaces of the via, wherein the via is formed within a dielectric layer and has the necking point protruding within the via, performing a selective deposition process to selectively deposit metal fill material on the exposed surface of the metal layer below the necking point, and performing a selectivity recovery process to oxidize by-products from the selective deposition process, and performing a full bottom fill process to fill a remainder of the via with the metal fill material.
    Type: Application
    Filed: March 21, 2024
    Publication date: September 25, 2025
    Inventors: Yao XU, Xi CEN, Kai WU, Insu HA, Rongjun WANG, Xianmin TANG
  • Patent number: 12351909
    Abstract: Methods of depositing a metal film are discussed. A metal film is formed on the bottom of feature having a metal bottom and dielectric sidewalls. Formation of the metal film comprises exposure to a metal precursor and an alkyl halide catalyst while the substrate is maintained at a deposition temperature. The metal precursor has a decomposition temperature above the deposition temperature. The alkyl halide comprises carbon and halogen, and the halogen comprises bromine or iodine.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: July 8, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Byunghoon Yoon, Liqi Wu, Joung Joo Lee, Kai Wu, Xi Cen, Wei Lei, Sang Ho Yu, Seshadri Ganguli
  • Publication number: 20250210381
    Abstract: The disclosure generally includes a heat reflection assembly for improved deposition uniformity in semiconductor manufacturing. In one embodiment, a heat reflection assembly for semiconductor manufacturing is provided. The heat reflection assembly includes a reflector plate and a first tuning element. The reflector plate includes a first surface having a first region with a first emissivity. The first tuning element is disposed on the first surface of the reflector plate. The first tuning element includes a reflecting surface having a second emissivity different than the first emissivity.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Inventors: Cheng CHENG, Dongming IU, Xi CEN, Kai WU, Yao XU
  • Publication number: 20250038051
    Abstract: A structure is provided including a substrate and a tungsten-containing layer. The tungsten-containing layer includes a nucleation layer disposed on the substrate and a bulk layer is disposed over the nucleation layer. The nucleation layer includes tungsten and the bulk layer includes about 0.1% to about 20% atomic molybdenum. The tungsten-containing layer includes a film stress of about 350 MPa to about 450 MPa.
    Type: Application
    Filed: October 7, 2024
    Publication date: January 30, 2025
    Inventors: Xi CEN, Kai WU, Dixiong WANG, Yi LUO
  • Patent number: 12191198
    Abstract: Apparatus and methods to provide electronic devices comprising tungsten film stacks are provided. A tungsten liner formed by physical vapor deposition is filled with a tungsten film formed by chemical vapor deposition directly over the tungsten liner.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 7, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Feihu Wang, Joung Joo Lee, Xi Cen, Zhibo Yuan, Wei Lei, Kai Wu, Chunming Zhou, Zhebo Chen
  • Patent number: 12159804
    Abstract: A structure is provided including a substrate and a tungsten-containing layer. The tungsten-containing layer includes a nucleation layer disposed on the substrate and a bulk layer is disposed over the nucleation layer. The nucleation layer includes tungsten and the bulk layer includes about 0.1% to about 20% atomic molybdenum. The tungsten-containing layer includes a film stress of about 350 MPa to about 450 MPa.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: December 3, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xi Cen, Kai Wu, Dixiong Wang, Yi Luo
  • Publication number: 20240371654
    Abstract: A method of filling a feature in a semiconductor structure with metal includes depositing a metal cap layer on a bottom surface of a feature formed within a dielectric layer and top surfaces of the dielectric layer, partially filling the feature from the bottom surface with a flowable polymer layer, performing a metal pullback process to remove the metal cap layer on the top surfaces of the dielectric layer selectively to the dielectric layer, wherein the metal pullback process includes a first etch process including a chemical etch process using molybdenum hexafluoride (MoF6) to remove the metal cap layer selectively to the dielectric layer, and a second etch process to remove residues on etched surfaces of the dielectric layer, removing the flowable polymer layer, pre-cleaning a surface of the metal cap layer, and filling the feature from the surface of the metal cap layer with metal fill material.
    Type: Application
    Filed: May 3, 2023
    Publication date: November 7, 2024
    Inventors: Qihao ZHU, Chi Hong CHING, Liqi WU, Tsungjui LIU, Gaurav THAREJA, Xinke WANG, Feng Q. LIU, Xi CEN, Kai WU, Yixiong YANG, Yuanhung LIU, Jiang LU, Rongjun WANG, Xianmin TANG
  • Patent number: 12094773
    Abstract: Method for forming tungsten gap fill on a structure, including high aspect ratio structures includes depositing a tungsten liner in the structure using a physical vapor deposition (PVD) process with high ionization and an ambient gas of argon or krypton. The PVD process is performed at a temperature of approximately 20 degrees Celsius to approximately 300 degrees Celsius. The method further includes treating the structure with a nitridation process and depositing bulk fill tungsten into the structure using a chemical vapor deposition (CVD) process to form a seam suppressed boron free tungsten fill. The CVD process is performed at a temperature of approximately 300 degrees Celsius to approximately 500 degrees Celsius and at a pressure of approximately 5 Torr to approximately 300 Torr.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: September 17, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xi Cen, Kai Wu, Min Heon, Wei Min Chan, Tom Ho Wing Yu, Peiqi Wang, Ju Ik Kang, Feihu Wang, Nobuyuki Sasaki, Chunming Zhou
  • Publication number: 20240282631
    Abstract: A method of filling a via having a necking point includes performing a pre-clean process to remove residues from an exposed surface of a metal layer at a bottom of a via and recover inner surfaces of the via, wherein the via is formed within a dielectric layer and has a necking point protruding within the via, performing a selective deposition process to partially fill the via with metal fill material from the exposed surface of the metal layer below the necking point, performing a liner deposition process to form a liner layer on exposed inner surfaces of the via, and performing a metal fill process to fill the via with the metal fill material.
    Type: Application
    Filed: January 22, 2024
    Publication date: August 22, 2024
    Inventors: Xi CEN, Kai WU, Yao XU, Yang LI, Meng ZHU, Insu HA, Jianqiu GUO, Chao LI, Rongjun WANG, Xianmin TANG
  • Publication number: 20240266215
    Abstract: A method of forming a structure on a substrate, includes forming a nucleation layer within an opening of the substrate within a processing chamber. The method further includes forming a passivation layer on at least a portion of the nucleation layer by introducing radical treatment into the processing chamber. The method further includes forming a tungsten fill layer within the opening over the passivation layer and the nucleation layer, wherein the tungsten fill layer is formed by a plurality of treatment cycles. Each treatment cycle includes pulsing a first gas at the substrate for a pulse time duration while concurrently flowing a second gas over the substrate, and purging the first gas and the second gas by flowing a purge gas over the substrate for a purge time duration.
    Type: Application
    Filed: February 8, 2023
    Publication date: August 8, 2024
    Inventors: Xi CEN, Yang LI, Kai WU, Mehran BEHDJAT, Jallepally RAVI
  • Publication number: 20240258109
    Abstract: A method of forming a structure on a substrate includes forming an adhesion layer on a substrate. The method further includes forming a tungsten containing layer in-situ with the adhesion layer. The tungsten containing layer is formed by a one-time soak process including soaking the substrate once, and only once, in a first gas, purging the first gas, and soaking the substrate once, and only once, in a second gas. The method further includes removing the tungsten containing layer from the adhesion layer.
    Type: Application
    Filed: December 7, 2023
    Publication date: August 1, 2024
    Inventors: Xi CEN, Kai WU, Min-Han LEE, Yang LI, Cheng CHENG, Zhixiu LIANG
  • Publication number: 20240209500
    Abstract: Embodiments herein are generally directed to electronic device manufacturing and, more particularly, to systems and methods for forming substantially void-free and seam-free tungsten features in a semiconductor device manufacturing scheme. In one embodiment, a substrate processing system features a processing chamber and a gas delivery system fluidly coupled to the processing chamber. The gas delivery system includes a first radical generator for use in a differential inhibition treatment process and a second radical generator for use in a chamber clean process.
    Type: Application
    Filed: May 6, 2021
    Publication date: June 27, 2024
    Inventors: Xi CEN, Wei Min CHAN, Kai WU, Peiqi WANG, Mingrui ZHAO, Michael C. KUTNEY, Kazuya DAITO, Harpreet SINGH
  • Patent number: 12014956
    Abstract: Some embodiments of the disclosure relate to methods for forming a bottom-up tungsten gapfill. Some embodiments of the disclosure relate to methods for reducing the deposition rate of tungsten by chemical vapor deposition. A molybdenum halide precursor is added to a tungsten halide precursor and a reductant. The co-flow of tungsten halide and molybdenum halide demonstrates either reduced or eliminated tungsten growth.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: June 18, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Xi Cen, Kai Wu
  • Publication number: 20240162089
    Abstract: A method of forming a structure on a substrate that includes forming a tungsten nucleation layer within at least one opening within a multi-tier portion of a substrate. The method includes exposing the nucleation layer to a nitrogen-containing gas to inhibit growth of the nucleation layer at narrow points within the at least one opening. The method includes exposing the at least one opening of the substrate to the tungsten-containing precursor gas to form a fill layer over the nucleation layer within the at least one opening. The method includes exposing the at least one opening to a molybdenum-containing gas to remove a tungsten nitride layer from the tungsten fill layer.
    Type: Application
    Filed: November 11, 2022
    Publication date: May 16, 2024
    Inventors: Dixiong WANG, Xi CEN, Kai WU, Peiqi WANG, Yang LI
  • Publication number: 20240047268
    Abstract: A method of forming a structure on a substrate includes forming a tungsten nucleation layer within at least one opening within a multi-tier portion of a substrate. The method includes exposing the nucleation layer a nitrogen-containing gas to inhibit growth of the nucleation layer at narrow portions within the at least one opening. The method includes exposing the at least one opening to the tungsten-containing precursor gas to form a fill layer over the nucleation layer within the at least one opening. The method includes exposing the at least one opening of the substrate to the nitrogen-containing gas or a nitrogen-containing plasma to inhibit growth of portions of the fill layer along the at least one opening.
    Type: Application
    Filed: July 17, 2023
    Publication date: February 8, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Peiqi WANG, Xi CEN, Dixiong WANG, Mingrui ZHAO, Yang LI, Kai WU
  • Patent number: D1066440
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: March 11, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Yang Li, Xi Cen, Kai Wu, Min-Han Lee, Mehran Behdjat