Abstract: A deep learning heterogeneous computing method based on layer-wide memory allocation, at least comprises steps of: traversing a neural network model so as to acquire a training operational sequence and a number of layers L thereof; calculating a memory room R1 required by data involved in operation at the ith layer of the neural network model under a double-buffer configuration, where 1?i?L; altering a layer structure of the ith layer and updating the training operational sequence; distributing all the data across a memory room of the CPU and the memory room of the GPU according to a data placement method; performing iterative computation at each said layer successively based on the training operational sequence so as to complete neural network training.

Abstract: A deep learning heterogeneous computing method based on layer-wide memory allocation, at least comprises steps of: traversing a neural network model so as to acquire a training operational sequence and a number of layers L thereof; calculating a memory room R1 required by data involved in operation at the ith layer of the neural network model under a double-buffer configuration, where 1?i?L; altering a layer structure of the ith layer and updating the training operational sequence; distributing all the data across a memory room of the CPU and the memory room of the GPU according to a data placement method; performing iterative computation at each said layer successively based on the training operational sequence so as to complete neural network training.

Abstract: A method of processing a semiconductor wafer may include providing a rotatably alignable photolithography mask that includes different mask images. Each mask image may be in a corresponding different mask sector. The method may also include performing a series of exposures with the rotatably alignable photolithography mask at different rotational alignments with respect to the semiconductor wafer so that the different mask images produce at least one working semiconductor wafer sector, and at least one non-working semiconductor wafer sector.

Abstract: A method of processing a semiconductor wafer may include providing a rotatably alignable photolithography mask that includes different mask images. Each mask image may be in a corresponding different mask sector. The method may also include performing a series of exposures with the rotatably alignable photolithography mask at different rotational alignments with respect to the semiconductor wafer so that the different mask images produce at least one working semiconductor wafer sector, and at least one non-working semiconductor wafer sector.