Abstract: A method for cleaning semiconductor substrate without damaging patterned structure on the semiconductor substrate using ultra/mega sonic device comprises applying liquid into a space between a substrate and an ultra/mega sonic device; setting an ultra/mega sonic power supply at frequency f1 and power P1 to drive the ultra/mega sonic device; before bubble cavitation in the liquid damaging patterned structure on the substrate, setting the ultra/mega sonic power supply at zero output; after temperature inside bubble cooling down to a set temperature, setting the ultra/mega sonic power supply at frequency f1 and power P1 again; detecting power on time at power P1 and frequency f1 and power off time separately or detecting amplitude of each waveform output by the ultra/mega sonic power supply; comparing the detected power on time with a preset time ?1, or comparing the detected power off time with a preset time ?2, or comparing detected amplitude of each waveform with a preset value, if the detected power on time

Abstract: Embodiments of the invention are directed to systems and methods for conducting a transaction utilizing a cryptocurrency. The user may fund a cryptocurrency account with his pre-existing cryptocurrency. An issuer may purchase cryptocurrency within a cryptocurrency exchange. The user may then utilize a payment device (e.g., a Crypto Debit Card) that is associated with a cryptocurrency balance to conduct a transaction with a merchant for goods and/or services. An authorization request message may be transmitted to the authorizing entity computer. The authorizing entity computer may determine a cryptocurrency amount corresponding to the fiat currency transaction amount of the authorization request message. A sell request message may be transmitted to an exchange that facilitates the sale of the cryptocurrency amount.

Abstract: A wireless transmit/receive unit (WTRU) may receive a constellation symbol that includes indications that each are associated with a respective WTRU of a plurality of WTRUs. The WTRU may determine that a first weight associated with a first indication of the indications is different than a second weight associated with a second indication of the indications. The indications may comprise indications of bits modulated at a multi-user constellation bit division multiple access modulator (MU-CBDMAM).

Abstract: A bubble detection device and a sample processing instrument are provided. The bubble detection device includes a body, a cover and a detection circuit board. The body includes a bottom wall and first and second side walls respectively extending from two sides of the bottom wall. The bottom, first and second side walls define a groove for accommodating a sample pipe of a sample processing instrument, and first and second holes are respectively provided in the first and second side walls to allow light from a light source to pass through the sample pipe. The cover includes a top portion for covering the groove and first and second side portions attached to the body. The detection circuit board includes the light source and a photoelectric sensor and is attached to the body such that they are aligned with the first and second holes respectively to sense intensity of the light passing through the sample pipe. The sample processing instrument includes the bubble detection device.

Abstract: An apparatus for controlling access to a memory device comprising rows of memory units is provided. The apparatus comprises: an operation monitor configured to track memory operations to the rows of memory units of the memory device; a row hammer counter configured to determining, for each of the rows of memory units, row hammer effects experienced by the row of memory units due to the memory operations to the other rows of memory units of the memory device; a mitigation module configured to initiate, for each of the rows of memory units, row hammer mitigation in case that accumulated row hammer effects experienced by the row of memory units reach a predetermined threshold; and a virtual host module configured to perform the row hammer mitigation targeting a row of memory units in response to the initiation of row hammer mitigation for the row of memory units by the mitigation module.

Abstract: A first device is logged in with a first user account. The first device displays an avatar of a second user account in a first user interface of the first device. In response to an interaction instruction triggered on the avatar of the second user account, the first device generates an interaction message according to a first field corresponding to the first user account, an action description field corresponding to the interaction instruction, and a second field corresponding to the second user account. The first device transmits the interaction message to a second device that is logged in with the second user account.

Abstract: Some embodiments provide a method of identifying packet latency in a software defined datacenter (SDDC) that includes a network and multiple host computers executing multiple machines. At a first host computer, the method identifies and stores (i) multiple time values associated with several packet processing operations performed on a particular packet sent by a first machine executing on the first host computer, and (ii) a time value associated with packet transmission through the SDDC network from the first host computer to a second host computer that is a destination of the particular packet. The method provides the stored time values to a set of one or more controllers to process to identify multiple latencies experienced by multiple packets processed in the SDDC.

Abstract: A system for controlling damages in cleaning a semiconductor wafer comprising features of patterned structures, the system comprising: a wafer holder for temporary restraining a semiconductor wafer during a cleaning process; an inlet for delivering a cleaning liquid over a surface of the semiconductor wafer; a sonic generator configured to alternately operate at a first frequency and a first power level for a first predetermined period of time and at a second frequency and a second power level for a second predetermined period of time, to impart sonic energy to the cleaning liquid, the first predetermined period of time and the second predetermined period of time consecutively following one another; and a controller programmed to provide the cleaning parameters, wherein at least one of the cleaning parameters is determined such that a percentage of damaged features as a result of the imparting sonic energy is lower than a predetermined threshold.

Abstract: Disclosed in the present invention are an energy-saving dishwasher and a control method therefor. The inner container is arranged inside the housing, the inner container is internally provided with a manifold type dish rack for placing dishes and spraying steam to perform steam cleaning on the dishes, and the manifold type dish rack is placed on a supporting frame fixed to the inner container. A water storage tank, a steam/hot water integrated generating device and a water pump are arranged below the inner container, and the steam/hot water integrated generating device includes a generating assembly and a control assembly. The manifold type dish rack is configured to place the dishes and simultaneously sprays steam to clean the dishes. The steam/hot water integrated generating device is configured to generate steam and hot water, heating is performed to generate the steam, and then relative cooling is performed to generate the hot water.

Abstract: The present invention relates to the treatment or management of autoimmune disorders, such as autoimmune disorders caused by autoreactive B lineage cells, e.g. anti-neutrophil cytoplasmic antibody (ANCA)-associated vasculitis (AAV).

Abstract: An apparatus for controlling access to a memory device comprising rows of memory units is provided. The apparatus comprises: an operation monitor configured to track memory operations to the rows of memory units of the memory device; a row hammer counter configured to determining, for each of the rows of memory units, row hammer effects experienced by the row of memory units due to the memory operations to the other rows of memory units of the memory device; a mitigation module configured to initiate, for each of the rows of memory units, row hammer mitigation in case that accumulated row hammer effects experienced by the row of memory units reach a predetermined threshold; and a virtual host module configured to perform the row hammer mitigation targeting a row of memory units in response to the initiation of row hammer mitigation for the row of memory units by the mitigation module.

Abstract: The present application provides a memory device.

Abstract: A memory device with modular design and the memory system comprising the same is disclosed. The memory device comprises a substrate plate having a front edge, a rear edge opposite to the front edge, and a top side and a bottom side which are opposite to each other and extend between the front edge and the rear edge; an edge connector positioned at the rear edge and configured to connect to a host connector of a host device; a memory control module positioned on one of the top side and the bottom side of the substrate plate; at least one socket positioned on the top side of the substrate plate and configured to connect to at least one removable memory module; and wherein the memory controller module is electrically coupled to the edge connector and the at least one socket such that the at least one memory module can be accessible by the host device via the memory control module.

Abstract: An industrial 5G dynamic multi-priority multi-access method based on deep reinforcement learning includes the following steps: establishing an industrial 5G network model; establishing a dynamic multi-priority multi-channel access neural network model based on deep reinforcement learning; collecting state, action and reward information of multiple time slots of all industrial 5G terminals in the industrial 5G network as training data; training the neural network model by using the collected data until the packet loss ratio and end-to-end latency meet industrial communication requirements; collecting the state information of all the industrial 5G terminals in the industrial 5G network at the current time slot as the input of the neural network model; conducting multi-priority channel allocation; and conducting multi-access by the industrial 5G terminals according to a channel allocation result.

Abstract: A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers, later than the target access CS signal, a command and address (CA) signal for addressing and accessing the multiple memory cells of the target memory rank; and wherein the target local controller is configured to generate, in response to receiving the target access CS signal, a target CA on-die termination (ODT) instruction switching on target CA ODT at its CA input at least for a period when the

Abstract: A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers, later than the target access CS signal, a command and address (CA) signal for addressing and accessing the multiple memory cells of the target memory rank; and wherein the target local controller is configured to generate, in response to receiving the target access CS signal, a target CA on-die termination (ODT) instruction switching on target CA ODT at its CA input at least for a period when the

Abstract: A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a non-target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, one or more non-target access CS signals disabling target access to one or more non-target memory ranks of the first plurality of memory ranks coupled to the non-target local controller; and the memory controller being further configured to provide to a target local controller of the second plurality of local controllers, out of the first plurality of CS signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers a command and address (CA) sign

Abstract: The invention concerns a shelf-stable concentrate cooking aid comprising a reduced amount of natural MSG, IMP and GMP between 10 and 20% in weight of natural food derived acids and sugars and between 20 and 45% of naturally derived macromolecules.

Abstract: Compositions and methods are provided for modulating the physiological activation of tissue transglutaminase (TG2); which methods can include inhibiting the activation of TG2 associated with enteric inflammatory disorders, which disorders may include celiac disease, irritable bowel syndrome, Crohn's Disease, dermatitis herpetiformis, and the like. In other embodiments of the invention, methods are provided for reducing undesirable paracellular transport in enteric tissues, in particular the paracellular transport of molecules greater than about 500 mw, e.g. peptides, including without limitation immunogenic gluten peptides.

Abstract: Use of low dose streptozocin in the preparation of an animal model for screening drugs for treatment of antoimmune type 1 diabetes is disclosed, in which streptozocin is administrated intravenously at a dose of 15-30 mg/kg per time for 5 days and administrated again on the 7th day and 14th day after last time of offering drug. A method for preparing rhesus monkey model of autoimmune type 1 diabetes and autoimmune type 1 diabetes animal model obtained are also disclosed.