Abstract: The present invention discloses a fabrication method and use of a ?40 mm large-size and high-contrast fiber optic image inverter, belonging to the field of manufacturing of fiber optic imaging elements. The light-absorbing glass for preparing the ?40 mm large-size and high-contrast fiber optic image inverter consists of the following components in molar percentage: SiO2 60-69.9, Al2O3 1.0-10.0, B2O3 10.1-15.0, Na2O 1.0-8.0, K2O 3.0-10.0, MgO 0.1-1.0, CaO 0.5-5.0, ZnO 0-0.1, TiO2 0-0.1, ZrO2 0.1-1.0, Fe2O3 3.0-6.5, Co2O3 0.1-0.5, V2O5 0.51-1.5 and MoO3 0.1-1.0. The fiber optic image inverter has the advantages of low crosstalk of stray light, high resolution and high contrast.

Abstract: A signal width repair circuit and method, and an electronic device are provided. The signal width repair circuit includes: a delay unit, configured to receive an input signal, and delay the input signal for a preset duration to obtain a delayed signal, the input signal being a low-level signal; a signal reconstruction unit, configured to receive the input signal and the delayed signal, and repair the input signal and the delayed signal to obtain a repaired signal; and a signal selection unit, configured to receive the input signal and the repaired signal and select one of the input signal and the repaired signal for output, to obtain a target signal that has a width satisfying a preset width, the preset duration being equal to or greater than a duration with the preset width.

Abstract: A refresh address counting circuit, a refresh address counting method, and a refresh address read-write circuit are provided. The refresh address counting circuit includes: a self-oscillation clock generation circuit, configured to generate, in each of refresh cycles, a self-oscillation clock signal based on at least one array activation signal upon acquiring a refresh signal; a self-oscillation mask circuit, configured to generate a self-oscillation mask signal under a preset refresh command; and a refresh address counter, configured to counting a refresh address based on the self-oscillation clock signal and the self-oscillation mask signal and to output a self-oscillation refresh address.

Abstract: Embodiments of the present disclosure relate to an address selection circuit and a control method thereof, and a memory. The address selection circuit includes an address receiving circuit, a row hammer address generation circuit, and a decoding circuit. The address receiving circuit is configured to output a first address output signal in response to a first selection signal, where the first address output signal includes a received regular refresh address signal or an active address signal. The row hammer address generation circuit is configured to: generate a second address output signal and a row hammer address redundancy identifier according to the first selection signal, an actual active address signal, and the first address output signal. The decoding circuit is configured to: generate a target address and the actual active address signal according to the second address output signal and the row hammer address redundancy identifier.

Abstract: A preprocessing module receives a word line activation command and a clock signal and outputs a word line address corresponding to a current word line activation command as a word line address signal when a count value reaches a preset value. An address processing module counts all received word line address signals and outputs a word line address signal with the largest number of occurrences as a row hammer address. A first processing unit generates first and second supplementary refresh address according to the row hammer address. A second processing unit generates a normal refresh address according to a refresh command. A refresh unit performs a refresh operation according to an acquired address signal. A control unit selects to output a refresh address or control the refresh unit to select to receive a refresh address.

Abstract: A refresh circuit includes signal selector configured to select one of normal and redundant word line logical addresses as output, output signal of which is designated as first logical address; row address latch connected to output terminal of signal selector and configured to output row hammer address and row hammer flag signal according to first logical address; seed arithmetic unit connected to output terminal of row address latch and configured to generate seed address according to row hammer address; logical arithmetic unit connected to output terminal of seed arithmetic unit and configured to obtain row hammer refresh address according to seed address, row hammer refresh address is adjacent physical address of seed address; and pre-decode unit connected to output terminal of logical arithmetic unit and configured to receive row hammer refresh address, and convert it into physical address to be used by memory array of memory to perform refresh operation.

Abstract: The embodiments of the present disclosure provide a random number generation circuit, including: a random number generator, including a feedback module and a plurality of sequentially connected flip-flops, where an output terminal of a previous flip-flop being connected to an input terminal of a next flip-flop, the output terminal of each of the flip-flops serving as an output terminal of the random number generator, and an output terminal of the feedback module being connected to the input terminal of one of the flip-flops; the feedback module being configured to receive selection signals and select, on the basis of the selection signals, the output terminals of two of the flip-flops as input terminals of the feedback module; and the random number generator being configured to output a plurality of first random numbers corresponding to corresponding selection signals in each counting cycle.

Abstract: Embodiments of the present disclosure provide a random number generator circuit, including: a random number generator, configured to output a plurality of first random numbers in each counting cycle; a control signal generation module, configured to receive a trigger signal and output control signals corresponding to different first random numbers based on the trigger signal; and a multi-select module, configured to receive the first random number and the control signal corresponding to the first random number, based on the control signal to adjust at least one bit position of the first random number, obtain a second random number, and output a plurality of the second random numbers.

Abstract: A method for promoting germination of underground buds and growth of new-born root systems of ratoon sugarcane is to cut stubbles based on a depth survey of the stubbles of the ratoon sugarcane, particularly including steps of: for a ratoon sugarcane field after mechanical harvesting, cutting the stubbles with a sugarcane stubble cutting machine, and remaining underground stubbles of 5-7 cm after cutting; for a ratoon sugarcane field with manual harvesting, cutting the sugarcane with a hoe, and remaining underground stubbles of 10-12 cm after cutting, so as to realize sugarcane cutting and stubble cutting in one step; thereafter, applying fertilizers and pesticides, and hilling up, wherein the underground buds of the stubbles are controlled to be distributed 10-15 cm below ground after hilling up; and finally conducting whole film mulching. The present invention is advanced and practical, and easily used and promoted.

Abstract: There are provided a signal width repair circuit and method, and an electronic device. The signal width repair circuit includes: a delay circuit, configured to receive an input signal, and delay the input signal for a preset duration to obtain a delayed signal, the input signal being a high-level signal; a signal reconstruction circuit, configured to receive the input signal and the delayed signal, and repair the input signal and the delayed signal to obtain a repaired signal; and a signal selection circuit, configured to receive the input signal and the repaired signal and select one of the input signal and the repaired signal for output, to obtain a target signal that has a width satisfying a preset width, the preset duration being equal to or greater than a duration with the preset width.

Abstract: A refresh circuit includes signal selector configured to select one of normal and redundant word line logical addresses as output, output signal of which is designated as first logical address; row address latch connected to output terminal of signal selector and configured to output row hammer address and row hammer flag signal according to first logical address; seed arithmetic unit connected to output terminal of row address latch and configured to generate seed address according to row hammer address; logical arithmetic unit connected to output terminal of seed arithmetic unit and configured to obtain row hammer refresh address according to seed address, row hammer refresh address is adjacent physical address of seed address; and pre-decode unit connected to output terminal of logical arithmetic unit and configured to receive row hammer refresh address, and convert it into physical address to be used by memory array of memory to perform refresh operation.

Abstract: There are provided a signal width repair circuit and method, and an electronic device. The signal width repair circuit includes: a delay circuit, configured to receive an input signal, and delay the input signal for a preset duration to obtain a delayed signal, the input signal being a high-level signal; a signal reconstruction circuit, configured to receive the input signal and the delayed signal, and repair the input signal and the delayed signal to obtain a repaired signal; and a signal selection circuit, configured to receive the input signal and the repaired signal and select one of the input signal and the repaired signal for output, to obtain a target signal that has a width satisfying a preset width, the preset duration being equal to or greater than a duration with the preset width.

Abstract: A signal width repair circuit and method, and an electronic device are provided. The signal width repair circuit includes: a delay unit, configured to receive an input signal, and delay the input signal for a preset duration to obtain a delayed signal, the input signal being a low-level signal; a signal reconstruction unit, configured to receive the input signal and the delayed signal, and repair the input signal and the delayed signal to obtain a repaired signal; and a signal selection unit, configured to receive the input signal and the repaired signal and select one of the input signal and the repaired signal for output, to obtain a target signal that has a width satisfying a preset width, the preset duration being equal to or greater than a duration with the preset width.

Abstract: A method for promoting germination of underground buds and growth of new-born root systems of ratoon sugarcane is to cut stubbles based on a depth survey of the stubbles of the ratoon sugarcane, particularly including steps of: for a ratoon sugarcane field after mechanical harvesting, cutting the stubbles with a sugarcane stubble cutting machine, and remaining underground stubbles of 5-7 cm after cutting; for a ratoon sugarcane field with manual harvesting, cutting the sugarcane with a hoe, and remaining underground stubbles of 10-12 cm after cutting, so as to realize sugarcane cutting and stubble cutting in one step; thereafter, applying fertilizers and pesticides, and hilling up, wherein the underground buds of the stubbles are controlled to be distributed 10-15 cm below ground after hilling up; and finally conducting whole film mulching. The present invention is advanced and practical, and easily used and promoted.