Abstract: A polarizable ion-conducting material. The material contains mobile ions and a matrix formed of a polymer having ionic groups of a charge opposite to that of the mobile ions, wherein the material has a polarization of at least 0.2 mC/g, a capacitance of at least 0.1 mF/g, and a polarization retention time of at least 5 seconds. Also disclosed is a device containing such a polarizable ion-conducting material.

Abstract: A coated substrate includes a substrate and a coating containing a water insoluble polymer and a water soluble polymer, the two polymers, due to different water affinity, forming a nanosegregant on the substrate. Also disclosed are a method of preparing the above-described coated substrate and the use of this coated substrate in a solid-state supercapacitor.

Abstract: A polarizable ion-conducting material. The material contains mobile ions and a matrix formed of a polymer having ionic groups of a charge opposite to that of the mobile ions, wherein the material has a polarization of at least 0.2 mC/g, a capacitance of at least 0.1 mF/g, and a polarization retention time of at least 5 seconds. Also disclosed is a device containing such a polarizable ion-conducting material.

Abstract: A coated substrate includes a substrate and a coating containing a water insoluble polymer and a water soluble polymer, the two polymers, due to different water affinity, forming a nanosegregant on the substrate. Also disclosed are a method of preparing the above-described coated substrate and the use of this coated substrate in a solid-state supercapacitor.

Abstract: A method of fabricating an integrated circuit including strained silicon bearing regions. The method forms a blanket layer of material having an initial thickness overlying a source region, a drain region, and a gate structure of an MOS device to cover an upper surface of the gate structure, including the hard mask layer, to form a substantially planarized surface region from the blanket layer. The method removes a portion of the initial thickness of the blanket layer to remove the hard mask and expose a portion of the gate structure. In a preferred embodiment, the portion of the gate structure is substantially polysilicon material. The method introduces dopant impurities into the portion of the gate structure using at least an implantation process to dope the gate structure, while maintaining the source region and the gate region free from the dopant impurities.

Abstract: A semiconductor device, which has an improved contact structure. The device has a semiconductor substrate, e.g., silicon wafer. The device has a plurality of gate structures (e.g., MOS gate structures) formed on a portion of the semiconductor substrate. The device also has a gate dielectric layer and isolation structures, e.g., trench isolation. The device has a first interlayer dielectric (e.g., low K, BPSG, PSG, FSG) overlying the gate structures. In a preferred embodiment, the first interlayer dielectric layer has a substantially flat surface region. The device has a first copper interconnect layer overlying the substantially flat surface region of the first interlayer dielectric layer. The device also has a first low K dielectric layer overlying the first copper interconnect layer. A second copper interconnect layer is overlying the low K dielectric layer. In between the first and second copper layers is a copper ring structure enclosing an entirety of an inner region of the first low K dielectric layer.

Abstract: A method for forming a CMOS integrated circuit using strained silicon technology. The method forms a liner layer overlying the first gate structure and the second gate structure and overlying first source/drain regions in the first well region and second source/drain regions in the second well region. In a preferred embodiment, the method patterns A spacer dielectric layer to form first sidewall spacer structures on the first gate structure, including the first edges and to form the second sidewall spacer structures on the second gate structure, including the second edges, while using a portion of the liner layer as a stop layer. The method maintains the liner layer overlying the first source/drain regions and second source/drain regions during at least the patterning of the spacer dielectric layer according to a preferred embodiment.

Abstract: A method for forming CMOS integrated circuits. The method forms a blanket layer of silicon dioxide overlying an entirety of the surface region of a first well region and a second well region provided on a semiconductor substrate. The blanket layer of silicon dioxide is overlying the hard mask on the first gate structure and the second gate structure. The blanket layer of silicon dioxide is also overlying a region to be protected. Depending upon the embodiment, the region can be a sidewall spacer structure and portion of an MOS device on a peripheral region of the substrate. Of course, there can be other variations, modifications, and alternatives. The method protects the region to be protected using a masking layer, while the surface region of the first well region and the second well region being exposed.

Abstract: A method for forming a CMOS semiconductor wafer. The method includes providing a semiconductor substrate (e.g., silicon wafer) and forming a dielectric layer (e.g., silicon dioxide, silicon oxynitride) overlying the semiconductor substrate. The method includes forming a gate layer overlying the dielectric layer and patterning the gate layer to form a gate structure including edges. The method includes forming a dielectric layer overlying the gate structure to protect the gate structure including the edges. Preferably, the dielectric layer has a thickness of less than 40 nanometers. The method includes etching a source region and a drain region adjacent to the gate structure using the dielectric layer as a protective layer and depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region.

Abstract: Techniques for an integrated circuit device are provided. The integrated circuit device includes a substrate, an active circuit area, and a dielectric layer. A seal ring surrounds the active circuit area. At least one corner area of the integrated circuit includes a plurality of corner band stacks. Each of the plurality of corner band stacks is oriented at about a predetermined angle and extends from a first sawing trace to a second sawing trace. In a specific embodiment, if a structural fault in the at least one corner area occurs, the structural fault is predisposed to extend at about the predetermined angle.

Abstract: A partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material (e.g., silicon/germanium, silicon carbide) in an etched source region and an etched drain region. Preferably, the etched source region and the etched drain region are coupled to the gate structure.

Abstract: A semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device also has a gate structure including edges. A metal hard mask layer is overlying the gate structure. A dielectric layer is formed sidewall spacers on the edges of the gate structure to protect the gate structure including the edges. An exposed portion of the metal hard mask layer is overlying the gate structure. A silicon germanium fill material is provided in an etched source region and an etched drain region. The etched source region and the etched drain region are each coupled to the gate structure. The device has a strained channel region between the filled source region and the filled drain region from at least the silicon germanium material formed in the etched source region and the etched drain region. An electrical connection is coupled to the metal hard mask overlying the gate structure.

Abstract: An integrated circuit device structure with a novel contact feature. The structure includes a substrate, a dielectric layer overlying the substrate, and a metal interconnect overlying the dielectric layer. A first interlayer dielectric layer is formed surrounding the metal interconnect. A second interlayer dielectric layer of a predetermined thickness is overlying the first interlayer dielectric layer. A trench opening of a first width is formed within an upper portion of the second interlayer dielectric layer. A first barrier layer is within and is overlying the trench opening of the first width. A contact opening of a second width is within a lower portion of the second interlayer dielectric layer. The second width is less than the first width. The lower portion of the second interlayer dielectric layer is coupled to the upper portion of the second interlayer dielectric layer within the predetermined thickness of the second interlayer dielectric.

Abstract: An improved semiconductor integrated circuit device structure. The device structure includes a substrate. A thickness of first insulating material is overlying the substrate. A capacitor region within the thickness of the first insulating material and extends from a lower surface of the first insulating material to an upper surface of the first insulating material. The capacitor region includes a width, which extends from the lower surface to the upper surface. The width may vary slightly in some embodiments. The structure includes a contact region overlying the substrate within at least the capacitor region. A lower capacitor plate formed from a plurality of vertical metal structures defined within the capacitor region and connected to the contact region. Each of the plurality of vertical metal structures includes a width and a height. Each of the plurality of vertical metal structures is substantially parallel to each other along a length of the height of each of the vertical metal structures.