Abstract: A capacitor structure and a power converter are provided. The capacitor structure includes a parallel cell combination, and the parallel cell combination includes a plurality of cells and a plurality of current collectors. In the parallel cell combination: the cells are connected in parallel, and the poles connected in parallel are respectively connected with other devices through corresponding confluence points. Same poles of two adjacent cells are connected through a corresponding current collector, and the current-carrying specifications of each current collector is lower than the current-carrying requirements of a confluence point of a corresponding pole. That is to say, a conductor that implements the parallel connection of the cells is no longer a whole copper plate, but the individual current collectors, thus realizing the reduction of the cost of the conductor material.

Abstract: A capacitor structure and a power convertor are provided by the present disclosure. The capacitor structure includes a housing and at least one core arranged inside the housing, and two electrodes of the capacitor structure are respectively led out from two ends of the housing. Thus, the pole piece required in a case that electrodes are led from the same end of the housing is omitted, thereby saving material cost. Besides, the housing and the core are respectively hollow structures, and the internal heat of the capacitor structure can be ventilated and dissipated through the corresponding hollow part, thereby improving the heat dissipation performance of the capacitor structure. In addition, by arranging the fin heat dissipation teeth on the housing, the heat dissipation area can be increased to further improve the heat dissipation efficiency.

Abstract: A wire harness wall-passing structure and an installation method thereof. The wire harness wall-passing structure comprises: a sleeve pipe, a pouring sealant, and at least one sealing plug, wherein the sleeve pipe is alternately filled with the pouring sealant and the sealing plug along the axis direction of the sleeve pipe; and at least one first through hole formed in the sealing plug, and a wire harness which can penetrate through the pouring sealant and the first through hole in the sealing plug. According to the wire harness wall-passing structure, the sleeve pipe is filled with the pouring sealant and the sealing plug, so multi-stage sealing and multi-time sealing of the wire harness are achieved, the sealing performance of the wall-passing structure is greatly improved, and the wire harness wall-passing structure is more suitable for to-be-fixed devices such as a high pressure vessel.

Abstract: An inverter and an integrated platform having the same are provided. The inverter includes a cabinet having a cabinet door; an inverter body arranged in the cabinet; and a heat exchanger arranged on an outer side of the cabinet, where the inverter body has an alternating-current side, and the cabinet door is arranged on the alternating-current side or an opposite side of the alternating-current side of the inverter body.

Abstract: A specimen preparation method for eliminating a membrane penetration effect on a highly-weathered rock, wherein the method makes an originally uneven surface of a specimen smooth using a cured liquid latex as a filler, thereby eliminating a membrane penetration effect on a highly-weathered rock, and comprises the following specimen preparation steps: specimen cutting, pit filling, surface smoothing, specimen shaping and specimen loading.

Abstract: A power conversion device and an integrated machine are provided, The power conversion device includes a housing and a power converter. The power converter is arranged in the housing, and two ends, opposite to each other, of the power converter are respectively provided with a direct current wiring area and an alternate current wiring area. Two ends of the housing corresponding to the direct current wiring area and the alternate current wiring area each is provided with a movable door being capable of being opened and closed.

Abstract: In some embodiments, a memory controller in a processor includes a base value cache, a compressor, and a metadata cache. The compressor is coupled to the base value cache and the metadata cache. The compressor compresses a data block using at least a base value and delta values. The compressor determines whether the size of the data block exceeds a data block threshold value. Based on the determination of whether the size of the compressed data block generated by the compressor exceeds the data block threshold value, the memory controller transfers only a set of the compressed delta values to memory for storage. A decompressor located in the lower level cache of the processor decompresses the compressed data block using the base value stored in the base value cache, metadata stored in the metadata cache and the delta values stored in memory.

Abstract: A wire harness wall-passing structure and an installation method thereof. The wire harness wall-passing structure comprises: a sleeve pipe, a pouring sealant, and at least one sealing plug, wherein the sleeve pipe is alternately filled with the pouring sealant and the sealing plug along the axis direction of the sleeve pipe; and at least one first through hole is-formed in the sealing plug, and a wire harness which can penetrate through the pouring sealant and the first through hole in the sealing plug. According to the wire harness wall-passing structure, the sleeve pipe is filled with the pouring sealant and the sealing plug, so multi-stage sealing and multi-time sealing of the wire harness are achieved, the sealing performance of the wall-passing structure is greatly improved, and the wire harness wall-passing structure is more suitable for to-be-fixed devices such as a high pressure vessel.

Abstract: A capacitor structure and a power convertor are provided by the present disclosure. The capacitor structure includes a housing and at least one core arranged inside the housing, and two electrodes of the capacitor structure are respectively led out from two ends of the housing. Thus, the pole piece required in a case that electrodes are led from the same end of the housing is omitted, thereby saving material cost. Besides, the housing and the core are respectively hollow structures, and the internal heat of the capacitor structure can be ventilated and dissipated through the corresponding hollow part, thereby improving the heat dissipation performance of the capacitor structure. In addition, by arranging the fin heat dissipation teeth on the housing, the heat dissipation area can be increased to further improve the heat dissipation efficiency.

Abstract: A capacitor structure and a power converter are provided. The capacitor structure includes a parallel cell combination, and the parallel cell combination includes a plurality of cells and a plurality of current collectors. In the parallel cell combination: the cells are connected in parallel, and the poles connected in parallel are respectively connected with other devices through corresponding confluence points. Same poles of two adjacent cells are connected through a corresponding current collector, and the current-carrying specifications of each current collector is lower than the current-carrying requirements of a confluence point of a corresponding pole. That is to say, a conductor that implements the parallel connection of the cells is no longer a whole copper plate, but the individual current collectors, thus realizing the reduction of the cost of the conductor material.

Abstract: Systems, apparatuses, and methods for implementing memory request priority assignment techniques for parallel processors are disclosed. A system includes at least a parallel processor coupled to a memory subsystem, where the parallel processor includes at least a plurality of compute units for executing wavefronts in lock-step. The parallel processor assigns priorities to memory requests of wavefronts on a per-work-item basis by indexing into a first priority vector, with the index generated based on lane-specific information. If a given event is detected, a second priority vector is generated by applying a given priority promotion vector to the first priority vector. Then, for subsequent wavefronts, memory requests are assigned priorities by indexing into the second priority vector with lane-specific information. The use of priority vectors to assign priorities to memory requests helps to reduce the memory divergence problem experienced by different work-items of a wavefront.

Abstract: Wavefront loading in a processor is managed and includes monitoring a selected wavefront of a set of wavefronts. Reuse of memory access requests for the selected wavefront is counted. A cache hit rate in one or more caches of the processor is determined based on the counted reuse. Based on the cache hit rate, subsequent memory requests of other wavefronts of the set of wavefronts are modified by including a type of reuse of cache lines in requests to the caches. In the caches, storage of data in the caches is based on the type of reuse indicated by the subsequent memory access requests. Reused cache lines are protected by preventing cache line contents from being replaced by another cache line for a duration of processing the set of wavefronts. Caches are bypassed when streaming access requests are made.

Abstract: An inductor skeleton structure includes a pedestal and a main winding part. The pedestal includes a base, a fixing part and an auxiliary winding part, the fixing part is disposed on the base, and the auxiliary winding part is extended away from the base from a side surface; the main winding part has a main winding groove; the main winding part is fixed on a side of the base by the fixing part; the auxiliary winding part is used for winding an auxiliary coil capable of covering at least a portion of the welding surface; and the auxiliary coil is flush with or beyond the fitting surface.

Abstract: In some embodiments, a memory controller in a processor includes a base value cache, a compressor, and a metadata cache. The compressor is coupled to the base value cache and the metadata cache. The compressor compresses a data block using at least a base value and delta values. The compressor determines whether the size of the data block exceeds a data block threshold value. Based on the determination of whether the size of the compressed data block generated by the compressor exceeds the data block threshold value, the memory controller transfers only a set of the compressed delta values to memory for storage. A decompressor located in the lower level cache of the processor decompresses the compressed data block using the base value stored in the base value cache, metadata stored in the metadata cache and the delta values stored in memory.

Abstract: An electronic device includes a controller functional block and a computational functional block. During operation, while the computational functional block executes a test portion of a workload at at least one precision level, the controller functional block monitors a behavior of the computational functional block. Based on the behavior of the computational functional block while executing the test portion of the workload at the at least one precision level, the controller functional block selects a given precision level from among a set of two or more precision levels at which the computational functional block is to execute a remaining portion of the workload. The controller functional block then configures the computational block to execute the remaining portion of the workload at the given precision level.

Abstract: In some embodiments, a memory controller in a processor includes a base value cache, a compressor, and a metadata cache. The compressor is coupled to the base value cache and the metadata cache. The compressor compresses a data block using at least a base value and delta values. The compressor determines whether the size of the data block exceeds a data block threshold value. Based on the determination of whether the size of the compressed data block generated by the compressor exceeds the data block threshold value, the memory controller transfers only a set of the compressed delta values to memory for storage. A decompressor located in the lower level cache of the processor decompresses the compressed data block using the base value stored in the base value cache, metadata stored in the metadata cache and the delta values stored in memory.

Abstract: In some embodiments, a memory controller in a processor includes a base value cache, a compressor, and a metadata cache. The compressor is coupled to the base value cache and the metadata cache. The compressor compresses a data block using at least a base value and delta values. The compressor determines whether the size of the data block exceeds a data block threshold value. Based on the determination of whether the size of the compressed data block generated by the compressor exceeds the data block threshold value, the memory controller transfers only a set of the compressed delta values to memory for storage. A decompressor located in the lower level cache of the processor decompresses the compressed data block using the base value stored in the base value cache, metadata stored in the metadata cache and the delta values stored in memory.

Abstract: A specimen preparation method for eliminating a membrane penetration effect on a highly-weathered rock, wherein the method makes an originally uneven surface of a specimen smooth using a cured liquid latex as a filler, thereby eliminating a membrane penetration effect on a highly-weathered rock, and comprises the following specimen preparation steps: specimen cutting, pit filling, surface smoothing, specimen shaping and specimen loading.

Abstract: Systems, apparatuses, and methods for implementing memory request priority assignment techniques for parallel processors are disclosed. A system includes at least a parallel processor coupled to a memory subsystem, where the parallel processor includes at least a plurality of compute units for executing wavefronts in lock-step. The parallel processor assigns priorities to memory requests of wavefronts on a per-work-item basis by indexing into a first priority vector, with the index generated based on lane-specific information. If a given event is detected, a second priority vector is generated by applying a given priority promotion vector to the first priority vector. Then, for subsequent wavefronts, memory requests are assigned priorities by indexing into the second priority vector with lane-specific information. The use of priority vectors to assign priorities to memory requests helps to reduce the memory divergence problem experienced by different work-items of a wavefront.

Abstract: Wavefront loading in a processor is managed and includes monitoring a selected wavefront of a set of wavefronts. Reuse of memory access requests for the selected wavefront is counted. A cache hit rate in one or more caches of the processor is determined based on the counted reuse. Based on the cache hit rate, subsequent memory requests of other wavefronts of the set of wavefronts are modified by including a type of reuse of cache lines in requests to the caches. In the caches, storage of data in the caches is based on the type of reuse indicated by the subsequent memory access requests. Reused cache lines are protected by preventing cache line contents from being replaced by another cache line for a duration of processing the set of wavefronts. Caches are bypassed when streaming access requests are made.