Patents by Inventor XIANCHAO WANG

XIANCHAO WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240132536
    Abstract: The present invention provides a crystal of a compound represented by formula I as a 3-hydroxy-5-pregnane-20-one derivative and a preparation method therefor. Specifically, the present invention provides novel crystal forms A-C of the compound represented by formula I and a preparation method therefor. The novel crystal forms of the compound represented by formula I of the present invention have excellent thermal stability and mechanical stability, the preparation process thereof is simple, and the novel crystal forms have an excellent industrial implementation potential.
    Type: Application
    Filed: January 27, 2022
    Publication date: April 25, 2024
    Inventors: Fei LIU, Gang WU, Xianchao LI, Xiaobo WANG, Jinwei LIU
  • Publication number: 20230227374
    Abstract: A preparation method includes the following steps: Step (1): pressing and then drying body powder to form a green brick; Step (2): applying a ground coat on the surface of the green brick; Step (3): inkjet-printing a pattern on the surface of the green brick having the ground coat, and applying an isolation glaze; Step (4): applying a fully polished glaze on the surface of the green brick having the isolation glaze; and Step (5): drying, firing, and polishing the green brick having the fully polished glaze to obtain a hard wear-resistant polished glazed ceramic tile. The phase composition of the fired fully polished glaze is as follows: 10 to 20 percent by weight of corundum, 20 to 30 percent by weight of hyalophane, 0.5 to 1.0 percent by weight of hematite, and 50 to 68 percent by weight of amorphous phase.
    Type: Application
    Filed: December 24, 2020
    Publication date: July 20, 2023
    Inventors: Yijun LIU, Laifu DENG, Yuandong YANG, Xianchao WANG, Kelin ZHANG
  • Publication number: 20230192569
    Abstract: The present application provides a high-wear-resistance far-infrared ceramic polished glazed tile and preparation method therefor. The preparation method includes application of far-infrared overglaze, ink-jet printing, application of transparent far-infrared polished glaze and application of abrasion-resistant far-infrared polished glaze in sequence on a body, firing, and polishing. By adopting the far-infrared overglaze, the transparent far-infrared polished glaze and the abrasion-resistant far-infrared polished glaze in combination, the polished glaze tile can have a far-infrared function, high transparency, and high abrasion resistance.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 22, 2023
    Inventors: Yijun LIU, Yuandong YANG, Kelin ZHANG, Xianchao WANG, Lingyan HUANG
  • Publication number: 20220204416
    Abstract: A dry granular ceramic tile from a wet slurry spraying process and a preparation method thereof, comprises: applying an overglaze on a green body, applying a pattern by ink-jet printing, applying a dry granular glaze by bell-shaped spraying, and sintering to obtain ceramic tiles. The dry granular glaze contains: by mass percentage, dry granular frit A: 15%, dry granular frit B: 12% to 15%, dry granular frit C: 13% to 17%. The softening temperature of the dry granular frit A is 1135° C. to 1175° C., 980° C. to 1050° C. for the dry granular frit B, and 1020° C. to 1127° C. for the dry granular frit C. The dry granular frits used in the present invention adopts a combination of dry granular frits with three different melting points, and using such a matching method, it is convenient for the effective adjustment of the brick shape and the firing temperature during production.
    Type: Application
    Filed: November 21, 2019
    Publication date: June 30, 2022
    Inventors: Libiao XIAO, Qinggang WANG, Zengcheng QIN, Yuandong YANG, Xianchao WANG, Zhicong YAN, Kemu CHENG
  • Patent number: 11175229
    Abstract: A biosensor for detecting light signals emitted by a biological material is provided. The biosensor includes a light signal detector which comprises an array of light sensor pixels. The biosensor further includes a light signal filter layer disposed on a surface of the light sensor pixel array, a metal nanometer light focusing unit array layer, a grating array layer which comprises micro-gratings, and a biological material sample bearing area which comprises a plurality of sample gathering units. Each sample gathering unit aligns with one micro-grating and one metal nanometer light focusing unit in the vertical direction, and at least one of the light sensor pixels.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: November 16, 2021
    Assignee: GeneSense Technology Inc.
    Inventors: Xianchao Wang, Bingzhou Hong, Haochen Cui, Kun Luo, Yinghua Sun, Mei Yan
  • Patent number: 11125939
    Abstract: A waveguide filter sensing unit is provided. The waveguide sensing unit includes an input waveguide for receiving an optical signal and an interference waveguide region for filtering the optical signal to remove noise therein. The waveguide sensing unit further includes a cladding layer wrapping around the input waveguide and the interference waveguide region; and an optical signal detector converting the filtered optical signal into an electrical signal. The width of the input waveguide is smaller than that of the interference waveguide region, and the refractive index of the cladding layer is smaller than that of the input waveguide and the interference waveguide region.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: September 21, 2021
    Assignee: GeneSense Technology Inc.
    Inventors: Bingzhou Hong, Xianchao Wang, Haochen Cui, Tianshu Wang, Yinghua Sun, Mei Yan
  • Patent number: 10832920
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer on the semiconductor substrate and having an exposed portion of a lower surface, a capping layer on the first semiconductor layer, a second semiconductor layer below the capping layer and having a side surface substantially in full contact with the capping layer, a cavity defined by the first semiconductor layer, the second semiconductor layer, and the capping layer, and a through-hole passing through the capping layer and the second semiconductor layer and extending to the cavity.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: November 10, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Xianchao Wang
  • Patent number: 10773948
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure including a first electrode layer, forming a sacrificial layer on the first electrode layer, the sacrificial layer including a recess having a pointed bottom defining a depth, forming a second electrode layer on the sacrificial layer, the second electrode layer including a first opening exposing the recess, and forming a support layer filling the recess, the first opening, and on the second electrode layer. A portion of the support layer filling the recess forms a stopper having a height equal to the depth of the recess. The method also includes forming a second opening extending through the support layer and the second electrode layer and exposing a surface of the sacrificial layer, and removing a portion of the sacrificial layer to form a cavity.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: September 15, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Xianchao Wang
  • Publication number: 20200231429
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure including a first electrode layer, forming a sacrificial layer on the first electrode layer, the sacrificial layer including a recess having a pointed bottom defining a depth, forming a second electrode layer on the sacrificial layer, the second electrode layer including a first opening exposing the recess, and forming a support layer filling the recess, the first opening, and on the second electrode layer. A portion of the support layer filling the recess forms a stopper having a height equal to the depth of the recess. The method also includes forming a second opening extending through the support layer and the second electrode layer and exposing a surface of the sacrificial layer, and removing a portion of the sacrificial layer to form a cavity.
    Type: Application
    Filed: February 7, 2020
    Publication date: July 23, 2020
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Xianchao Wang
  • Patent number: 10584025
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure including a first electrode layer, forming a sacrificial layer on the first electrode layer, the sacrificial layer including a recess having a pointed bottom defining a depth, forming a second electrode layer on the sacrificial layer, the second electrode layer including a first opening exposing the recess, and forming a support layer filling the recess, the first opening, and on the second electrode layer. A portion of the support layer filling the recess forms a stopper having a height equal to the depth of the recess. The method also includes forming a second opening extending through the support layer and the second electrode layer and exposing a surface of the sacrificial layer, and removing a portion of the sacrificial layer to form a cavity.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: March 10, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Xianchao Wang
  • Publication number: 20190172721
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer on the semiconductor substrate and having an exposed portion of a lower surface, a capping layer on the first semiconductor layer, a second semiconductor layer below the capping layer and having a side surface substantially in full contact with the capping layer, a cavity defined by the first semiconductor layer, the second semiconductor layer, and the capping layer, and a through-hole passing through the capping layer and the second semiconductor layer and extending to the cavity.
    Type: Application
    Filed: February 7, 2019
    Publication date: June 6, 2019
    Applicants: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Xianchao Wang
  • Patent number: 10249508
    Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a first insulator layer on the first semiconductor layer, forming a patterned second semiconductor layer on the first insulator layer, the patterned second semiconductor layer having an actual thickness greater than a target thickness and exposing a portion of the first insulator layer; forming a second insulator layer as a spacer on the exposed portion of the first insulator layer, and performing an etching process on the patterned second semiconductor layer until the second semiconductor layer has the target thickness and concurrently removing the second insulator layer. The method can eliminate capillary etching of the spacer in a subsequent removal of the first insulator layer.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: April 2, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Xianchao Wang
  • Patent number: 10177027
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a substrate and a multilayer film having a step-shaped portion on the substrate; forming a protective layer covering the step-shaped portion of the multilayer film; forming a capping layer having a plurality of steps on the protective layer covering the semiconductor substrate; and removing at least one layer of the multilayer film to form a cavity that is defined by the capping layer and a remaining multilayer film that has the at least one layer removed. The thus formed semiconductor device does not have cracks in the steps of the capping layer when performing an etch process, thereby improving the performance of the semiconductor device.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: January 8, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Xianchao Wang
  • Publication number: 20180208455
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure including a first electrode layer, forming a sacrificial layer on the first electrode layer, the sacrificial layer including a recess having a pointed bottom defining a depth, forming a second electrode layer on the sacrificial layer, the second electrode layer including a first opening exposing the recess, and forming a support layer filling the recess, the first opening, and on the second electrode layer. A portion of the support layer filling the recess forms a stopper having a height equal to the depth of the recess. The method also includes forming a second opening extending through the support layer and the second electrode layer and exposing a surface of the sacrificial layer, and removing a portion of the sacrificial layer to form a cavity.
    Type: Application
    Filed: December 7, 2017
    Publication date: July 26, 2018
    Inventor: Xianchao Wang
  • Publication number: 20180068864
    Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a first insulator layer on the first semiconductor layer, forming a patterned second semiconductor layer on the first insulator layer, the patterned second semiconductor layer having an actual thickness greater than a target thickness and exposing a portion of the first insulator layer; forming a second insulator layer as a spacer on the exposed portion of the first insulator layer, and performing an etching process on the patterned second semiconductor layer until the second semiconductor layer has the target thickness and concurrently removing the second insulator layer. The method can eliminate capillary etching of the spacer in a subsequent removal of the first insulator layer.
    Type: Application
    Filed: August 17, 2017
    Publication date: March 8, 2018
    Inventor: XIANCHAO WANG
  • Publication number: 20180068888
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a substrate and a multilayer film having a step-shaped portion on the substrate; forming a protective layer covering the step-shaped portion of the multilayer film; forming a capping layer having a plurality of steps on the protective layer covering the semiconductor substrate; and removing at least one layer of the multilayer film to form a cavity that is defined by the capping layer and a remaining multilayer film that has the at least one layer removed. The thus formed semiconductor device does not have cracks in the steps of the capping layer when performing an etch process, thereby improving the performance of the semiconductor device.
    Type: Application
    Filed: August 17, 2017
    Publication date: March 8, 2018
    Inventor: XIANCHAO WANG