Patents by Inventor Xianda Ma

Xianda Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for filtering field programmable gate array input/output
    Patent number: 10592440
    Abstract: Systems and methods for adding a logic layer between FPGA I/O and the core logic of the FPGA. With the extra layer, users can monitor and/or modify the I/O to the FPGA. In addition, users can monitor and/or modify input/output to the core logics of the FPGA, thereby filtering both I/O to the FPGA and the logic blocks of the FPGA. With the filtering in place, a non-intrusive digital scope can be implemented which can, in turn, be used to create a “black box” regarding FPGA I/O during the occurrence of the catastrophic events within the system.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: March 17, 2020
    Assignee: Oracle International Corporation
    Inventors: Xianda Ma, Michael David Derbish, Cornelia Luise Edeltraut Koch-Stoschek, Rambabu Lolabattu, Simon yiu hoi Poon, Cheng Yang
  • SYSTEM AND METHOD FOR FILTERING FIELD PROGRAMMABLE GATE ARRAY INPUT/OUTPUT
    Publication number: 20190188160
    Abstract: Systems and methods for adding a logic layer between FPGA I/O and the core logic of the FPGA. With the extra layer, users can monitor and/or modify the I/O to the FPGA. In addition, users can monitor and/or modify input/output to the core logics of the FPGA, thereby filtering both I/O to the FPGA and the logic blocks of the FPGA. With the filtering in place, a non-intrusive digital scope can be implemented which can, in turn, be used to create a “black box” regarding FPGA I/O during the occurrence of the catastrophic events within the system.
    Type: Application
    Filed: February 21, 2019
    Publication date: June 20, 2019
    Applicant: Oracle International Corporation
    Inventors: Xianda Ma, Michael David Derbish, Cornelia Luise Edeltraut Koch-Stoschek, Rambabu Lolabattu, Simon yiu hoi Poon, Cheng Yang
  • System and method for filtering field programmable gate array input/output
    Patent number: 10248585
    Abstract: Systems and methods for adding a logic layer between FPGA I/O and the core logic of the FPGA. With the extra layer, users can monitor and/or modify the I/O to the FPGA. In addition, users can monitor and/or modify input/output to the core logics of the FPGA, thereby filtering both I/O to the FPGA and the logic blocks of the FPGA. With the filtering in place, a non-intrusive digital scope can be implemented which can, in turn, be used to create a “black box” regarding FPGA I/O during the occurrence of the catastrophic events within the system.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: April 2, 2019
    Assignee: Oracle International Corporation
    Inventors: Xianda Ma, Michael David Derbish, Cornelia Luise Edeltraut Koch-Stoschek, Rambabu Lolabattu, Simon yiu hoi Poon, Cheng Yang
  • SYSTEM AND METHOD FOR FILTERING FIELD PROGRAMMABLE GATE ARRAY INPUT/OUTPUT
    Publication number: 20170357603
    Abstract: Systems and methods for adding a logic layer between FPGA I/O and the core logic of the FPGA. With the extra layer, users can monitor and/or modify the I/O to the FPGA. In addition, users can monitor and/or modify input/output to the core logics of the FPGA, thereby filtering both I/O to the FPGA and the logic blocks of the FPGA. With the filtering in place, a non-intrusive digital scope can be implemented which can, in turn, be used to create a “black box” regarding FPGA I/O during the occurrence of the catastrophic events within the system.
    Type: Application
    Filed: June 14, 2016
    Publication date: December 14, 2017
    Applicant: Oracle International Corporation
    Inventors: Xianda Ma, Michael David Derbish, Cornelia Luise Edeltraut Koch-Stoschek, Rambabu Lolabattu, Simon yiu hoi Poon, Cheng Yang
  • Method of manufacturing semiconductor having group II-group VI compounds doped with nitrogen
    Patent number: 6852614
    Abstract: A method of making a semiconductor comprises depositing a group II-group VI compound onto a substrate in the presence of nitrogen using sputtering to produce a nitrogen-doped semiconductor. This method can be used for making a photovoltaic cell using sputtering to apply a back contact layer of group II-group VI compound to a substrate in the presence of nitrogen, the back coating layer being doped with nitrogen. A semiconductor comprising a group II-group VI compound doped with nitrogen, and a photovoltaic cell comprising a substrate on which is deposited a layer of a group II-group VI compound doped with nitrogen, are also included.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: February 8, 2005
    Assignee: University of Maine
    Inventors: Alvin D. Compaan, Kent J. Price, Xianda Ma, Konstantin Makhratchev