Abstract: Method, apparatus, and system for inspecting a cathode electrode plate of a composite material tape are provided. The method includes: using a camera apparatus to photograph a composite material tape being transported on a laminator to obtain an inspection image covering the composite material tape, where the inspection image includes a cathode electrode plate body region; extracting the cathode electrode plate body region from the inspection image; and inspecting the cathode electrode plate body region to determine a metal leakage defect existing in the cathode electrode plate body region. In the technical solution of the embodiments of this application, an inspection can be performed on a composite material tape being transported on a laminator, so that a metal leakage defect existing on a cathode electrode plate can be detected in real time in the production process of a laminated cell assembly.

Abstract: A method for fabricating a microlens array includes: step S1, providing a first substrate, and forming a patterned mask layer on the first substrate; step S2, etching the first substrate to form spaced grooves; step S3, removing the patterned mask layer; step S4, attaching a photoresist layer to the upper surface of the first substrate; step S5, softening the photoresist layer so that it adheres to the inner wall of the groove to form a concave smooth surface; step S6, solidifying the photoresist layer to form a working mold; applying an adhesive material and the working mold through the second substrate. The microlens array is produced by pressing the mold together or injecting PDMS material into the surface of the working mold.

Abstract: A method of fabricating vertical cavity surface emitting laser, comprising: providing a first substrate formed with a dielectric DBR and a first bonding layer, and a second substrate formed with a etch-stop layer, a heavily doped layer, an active region, a current-confinement layer, and an arsenide DBR firstly, then sticking a third substrate on the arsenide DBR, then removing the second substrate and the etch-stop layer, next bonding the heavily doped layer to the dielectric DBR, next removing the third substrate, finally forming a p-type electrode contact and an n-type electrode contact.

Abstract: An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a buffer layer, a first barrier layer, a second barrier layer, a first source, a first drain a first gate, a second source, a second drain, and a second gate. The buffer layer is on the substrate. The first barrier layer is on the buffer layer, and the second barrier layer is on the first barrier layer. The second barrier layer covers a portion of the first barrier layer. The first source, the first drain, and the first gate are on the first barrier layer, and the second source, the second drain, and the second gate are on the second banner layer.

Abstract: A method of fabricating vertical cavity surface emitting laser, comprising: providing a first substrate formed with a dielectric DBR and a first bonding layer, and a second substrate formed with a etch-stop layer, a heavily doped layer, an active region, a current-confinement layer, and an arsenide DBR firstly, then sticking a third substrate on the arsenide DBR, then removing the second substrate and the etch-stop layer, next bonding the heavily doped layer to the dielectric DBR, next removing the third substrate, finally forming a p-type electrode contact and an n-type electrode contact.

Abstract: The present application provides a semiconductor device and a method for manufacturing the same. The method includes: sequentially forming a buffer layer and a barrier layer on a substrate, wherein a two-dimensional electron gas is formed between the buffer layer and the barrier layer; etching a source region and a drain region of the barrier layer to form a trench on the buffer layer, and doped layers are formed on the trench; forming a passivation layer on the barrier layer and the doped layers, and etching the passivation layer to expose a portion of the barrier layer, wherein the portion of the barrier layer is in contact with the doped layers; and doping ions into a portion of the buffer layer in contact with the portion of the buffer layer.

Abstract: An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a first buffer layer, a first barrier layer, a first channel layer, a first source, a first drain, a first gate, a second buffer layer, a second barrier layer, a second channel layer, a second source, a second drain, and a second gate. The first buffer layer is on the substrate. The first barrier layer is on a first area of the first buffer layer, the first channel layer is on the first barrier layer, and the first source, the first drain, and the first gate are on the first channel layer. The second buffer layer is on a second area of the first buffer layer, the second bather layer is on the second buffer layer, the second channel layer is on the second barrier layer, and the second source, the second drain, and the second gate are on the second channel layer.

Abstract: A method of fabricating a high-crystalline-quality and high-uniformity AlN layer within a high electron mobility transistor (HEMT) device with a metalorganic chemical vapor deposition (MOCVD) technique, includes: raising a temperature of a substrate to an ultra-high growth temperature; and supplying an Al source and an N source in pulses over the substrate under the ultra-high growth temperature, wherein the ultra-high growth temperature is at least 1300° C. At least for a first predetermined period of time in each cycle of the pulses, the Al source is switched on when the N source is switched off.

Abstract: An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a first buffer layer, a first barrier layer, a first channel layer, a first source, a first drain, a first gate, a second buffer layer, a second barrier layer, a second channel layer, a second source, a second drain, and a second gate. The first buffer layer is on the substrate. The first barrier layer is on a first area of the first buffer layer, the first channel layer is on the first barrier layer, and the first source, the first drain, and the first gate are on the first channel layer. The second buffer layer is on a second area of the first buffer layer, the second bather layer is on the second buffer layer, the second channel layer is on the second barrier layer, and the second source, the second drain, and the second gate are on the second channel layer.

Abstract: An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a buffer layer, a first barrier layer, a second barrier layer, a first source, a first drain a first gate, a second source, a second drain, and a second gate. The buffer layer is on the substrate. The first barrier layer is on the buffer layer, and the second barrier layer is on the first barrier layer. The second barrier layer covers a portion of the first barrier layer. The first source, the first drain, and the first gate are on the first barrier layer, and the second source, the second drain, and the second gate are on the second banner layer.

Abstract: The present invention provides an integrated enhancement/depletion mode HEMT and a method for manufacturing the same, by which method an enhancement mode transistor and a depletion mode transistor can be integrated together, which is beneficial for increasing the application of gallium nitride HEMT devices and improving the characteristics of circuits, and lay a foundation for realizing monolithic integration of high-speed digital/analog mixed signal radio frequency circuits. At the same time, by using a regrowth technology of a barrier layer, electrons generated by impurities are made part of a conductive channel, thus the concentration of the two-dimensional electron gas is increased, and the conductive performance is improved while preventing excessive electrons from interfering with the devices.

Abstract: The present invention provides an integrated enhancement/depletion mode HEMT and a method for manufacturing the same, according to which an enhancement mode transistor and a depletion mode transistor can be integrated together, which is beneficial for increasing the application of gallium nitride HEMT devices and improving the characteristics of circuits, and lay a foundation for realizing monolithic integration of high-speed digital/analog mixed signal radio frequency circuits. At the same time, by utilizing the regrowth of the buffer layer and the doping requirements, electrons generated by impurities are made part of the doping layer, thus the doping concentration is improved while preventing excessive electrons from interfering with the devices.

Abstract: The present invention relates to a method for manufacturing a nitrogen-face polarity gallium nitride epitaxial structure, which includes: providing a gallium nitride template which includes a substrate and a first nitrogen-face polarity gallium nitride layer positioned on the substrate; re-growing the gallium nitride on a surface of the first nitrogen-face polarity gallium nitride layer to form a second nitrogen-face polarity gallium nitride layer; and sequentially growing a barrier layer and a channel layer on the second nitrogen-face polarity gallium nitride layer. The method for manufacturing the nitrogen-face polarity gallium nitride epitaxial structure provided by the present application enables a simple growth of the nitrogen-face polarity gallium nitride, can effectively eliminate the radio frequency dispersion phenomenon, and is beneficial to large-scale production and utilization of the nitrogen-face polarity gallium nitride epitaxial structure.

Abstract: A method for recovering carbon-face-polarized silicon carbide substrates, including: providing an epitaxial structure, the epitaxial structure includes a carbon-face-polarized silicon carbide substrate to be recovered, as well as a nitrogen-face-polarized gallium nitride buffer layer, a barrier layer and a nitrogen-face-polarized gallium nitride channel layer that are sequentially deposited on the silicon carbide substrate; removing the nitrogen-face-polarized gallium nitride buffer layer, the barrier layer and the nitrogen-face-polarized gallium nitride channel layer by wet etching; and cleaning and blowing dry the carbon-face-polarized silicon carbide substrate.

Abstract: A method of fabricating a semiconductor structure includes: growing a dielectric layer on a substrate; defining an epitaxial region and a gap region on the dielectric layer; etching a dielectric layer of the epitaxial region to expose the substrate; sequentially growing a gallium nitride buffer layer and an aluminum gallium nitride barrier layer on the exposed substrate. The method of fabricating a semiconductor structure provided by the present application divides the aluminum gallium nitride barrier layer into a plurality of independent portions, thus preventing the microcracks from occurring in the aluminum gallium nitrogen film while increasing the aluminum component, thereby improving the yield rate and reliability of the device.

Abstract: The present application provides a semiconductor device and a method for manufacturing the same. The method includes: sequentially forming a buffer layer and a barrier layer on a substrate, wherein a two-dimensional electron gas is formed between the buffer layer and the barrier layer; etching a source region and a drain region of the barrier layer to form a trench on the buffer layer, and doped layers are formed on the trench; forming a passivation layer on the barrier layer and the doped layers, and etching the passivation layer to expose a portion of the barrier layer, wherein the portion of the barrier layer is in contact with the doped layers; and doping ions into a portion of the buffer layer in contact with the portion of the buffer layer.

Abstract: The present application provides a semiconductor device and a method for manufacturing the same. The method includes: sequentially forming a buffer layer and a barrier layer on a substrate, wherein a two-dimensional electron gas is formed between the buffer layer and the barrier layer; etching a source region and a drain region of the barrier layer to form a trench on the buffer layer, and doped layers are formed on the trench; forming a passivation layer on the barrier layer and the doped layers, and etching the passivation layer to expose a portion of the barrier layer, wherein the portion of the barrier layer is in contact with the doped layers; and doping ions into a portion of the buffer layer in contact with the portion of the buffer layer.

Abstract: A method for recovering carbon-face-polarized silicon carbide substrates, including: providing an epitaxial structure, the epitaxial structure includes a carbon-face-polarized silicon carbide substrate to be recovered, as well as a nitrogen-face-polarized gallium nitride buffer layer, a barrier layer and a nitrogen-face-polarized gallium nitride channel layer that are sequentially deposited on the silicon carbide substrate; removing the nitrogen-face-polarized gallium nitride buffer layer, the barrier layer and the nitrogen-face-polarized gallium nitride channel layer by wet etching; and cleaning and blowing dry the carbon-face-polarized silicon carbide substrate.

Abstract: A method of fabricating a semiconductor structure includes: growing a dielectric layer on a substrate; defining an epitaxial region and a gap region on the dielectric layer; etching a dielectric layer of the epitaxial region to expose the substrate; sequentially growing a gallium nitride buffer layer and an aluminum gallium nitride barrier layer on the exposed substrate. The method of fabricating a semiconductor structure provided by the present application divides the aluminum gallium nitride barrier layer into a plurality of independent portions, thus preventing the microcracks from occurring in the aluminum gallium nitrogen film while increasing the aluminum component, thereby improving the yield rate and reliability of the device.

Abstract: A method of fabricating a high-crystalline-quality and high-uniformity AlN layer within a high electron mobility transistor (HEMT) device with a metalorganic chemical vapor deposition (MOCVD) technique, includes: raising a temperature of a substrate to an ultra-high growth temperature; and supplying an Al source and an N source in pulses over the substrate under the ultra-high growth temperature, wherein the ultra-high growth temperature is at least 1300° C. At least for a first predetermined period of time in each cycle of the pulses, the Al source is switched on when the N source is switched off.