Patents by Inventor Xianfu Zhang
Xianfu Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11809730Abstract: A storage controller is coupled to a memory, and the memory includes a first storage area and a second storage area. The storage controller includes a data migration circuit and a data operation determining circuit. The data migration circuit is configured to generate a migration signal, to migrate data in the first storage area to the second storage area. In a process in which the data migration circuit migrates all the data in the first storage area to the second storage area, the data operation determining circuit is configured to: receive and monitor a data operation signal input to the memory, and output a data migration failure signal when detecting that the data operation signal is a data modify signal with respect to the first storage area.Type: GrantFiled: July 30, 2021Date of Patent: November 7, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Xianfu Zhang, Zhengbo Wang
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Publication number: 20210357141Abstract: A storage controller is coupled to a memory, and the memory includes a first storage area and a second storage area. The storage controller includes a data migration circuit and a data operation determining circuit. The data migration circuit is configured to generate a migration signal, to migrate data in the first storage area to the second storage area. In a process in which the data migration circuit migrates all the data in the first storage area to the second storage area, the data operation determining circuit is configured to: receive and monitor a data operation signal input to the memory, and output a data migration failure signal when detecting that the data operation signal is a data modify signal with respect to the first storage area.Type: ApplicationFiled: July 30, 2021Publication date: November 18, 2021Inventors: Xianfu ZHANG, Zhengbo WANG
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Patent number: 10482027Abstract: This application relates to a cache management method and apparatus, so as to improve cache efficiency and reduce waste of cache resources. The cache management method provided in this application includes: after receiving a to-be-processed command, determining a quantity of cache units needed by the to-be-processed command; if the quantity of cache units needed by the to-be-processed command is one, searching for, based on a cache unit pair first state table, a pair of cache units in which only one cache unit is idle, and allocating the idle cache unit in the pair of cache units to the to-be-processed command; and if the quantity of cache units needed by the to-be-processed command is two, searching for and allocating, based on a cache unit pair second state table in a clock cycle, a pair of cache units in which two cache units are both idle to the to-be-processed command.Type: GrantFiled: December 27, 2016Date of Patent: November 19, 2019Assignee: Huawei Technologies Co., Ltd.Inventors: Xianfu Zhang, Qiang Wang
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Patent number: 10430344Abstract: The present invention provides a memory resource management method and apparatus. The method includes: first, determining a recyclable cache unit according to first indication information and second indication information that correspond to each cache unit, where the first indication information and the second indication information both include at least one bit, the first indication information indicates whether the cache unit is occupied, and the second indication information indicates a quantity of cache unit recycling periods for which the cache unit has been occupied; and then, recycling the recyclable cache unit. A quantity of cache unit recycling periods is set, and when a time for which a cache unit has been occupied reaches the preset quantity of cache unit recycling periods, the cache unit is forcibly recycled, thereby effectively improving cache unit utilization and improving system bandwidth utilization.Type: GrantFiled: December 28, 2016Date of Patent: October 1, 2019Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Xianfu Zhang, Qiang Wang
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Patent number: 10261694Abstract: Embodiments of the present invention provide a data storage method and system. The data storage method is applied to a data storage system, the data storage system includes a packet processing device, a processor, an off-chip memory, and a first counter corresponding to the off-chip memory, the off-chip memory is configured to store a count value of the first counter corresponding to the off-chip memory, and the packet processing device is configured to receive and process a service packet, count the service packet by using the first counter, and maintain an original address at which the count value of the first counter is stored in the off-chip memory. The method includes: scrambling, by the processor, the original address to obtain a scrambled address; and storing, by the processor, the count value of the first counter in a storage space corresponding to the scrambled address in the off-chip memory.Type: GrantFiled: December 28, 2016Date of Patent: April 16, 2019Assignee: Huawei Technologies Co., Ltd.Inventor: Xianfu Zhang
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Publication number: 20170192675Abstract: Embodiments of the present invention provide a data storage method and system. The data storage method is applied to a data storage system, the data storage system includes a packet processing device, a processor, an off-chip memory, and a first counter corresponding to the off-chip memory, the off-chip memory is configured to store a count value of the first counter corresponding to the off-chip memory, and the packet processing device is configured to receive and process a service packet, count the service packet by using the first counter, and maintain an original address at which the count value of the first counter is stored in the off-chip memory. The method includes: scrambling, by the processor, the original address to obtain a scrambled address; and storing, by the processor, the count value of the first counter in a storage space corresponding to the scrambled address in the off-chip memory.Type: ApplicationFiled: December 28, 2016Publication date: July 6, 2017Inventor: Xianfu Zhang
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Publication number: 20170192899Abstract: This application relates to a cache management method and apparatus, so as to improve cache efficiency and reduce waste of cache resources. The cache management method provided in this application includes: after receiving a to-be-processed command, determining a quantity of cache units needed by the to-be-processed command; if the quantity of cache units needed by the to-be-processed command is one, searching for, based on a cache unit pair first state table, a pair of cache units in which only one cache unit is idle, and allocating the idle cache unit in the pair of cache units to the to-be-processed command; and if the quantity of cache units needed by the to-be-processed command is two, searching for and allocating, based on a cache unit pair second state table in a clock cycle, a pair of cache units in which two cache units are both idle to the to-be-processed command.Type: ApplicationFiled: December 27, 2016Publication date: July 6, 2017Applicant: HUAWEI TECHNOLOGIES CO., LTDInventors: Xianfu ZHANG, Qiang Wang
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Publication number: 20170185522Abstract: The present invention provides a memory resource management method and apparatus. The method includes: first, determining a recyclable cache unit according to first indication information and second indication information that correspond to each cache unit, where the first indication information and the second indication information both include at least one bit, the first indication information indicates whether the cache unit is occupied, and the second indication information indicates a quantity of cache unit recycling periods for which the cache unit has been occupied; and then, recycling the recyclable cache unit. A quantity of cache unit recycling periods is set, and when a time for which a cache unit has been occupied reaches the preset quantity of cache unit recycling periods, the cache unit is forcibly recycled, thereby effectively improving cache unit utilization and improving system bandwidth utilization.Type: ApplicationFiled: December 28, 2016Publication date: June 29, 2017Inventors: Xianfu Zhang, Qiang Wang