Patents by Inventor Xiang Hui ZHAO

Xiang Hui ZHAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11876016
    Abstract: Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method for forming a hole structure having a first hole portion and a second hole portion connected to and over the first portion in a stack structure of a semiconductor device includes determining a hard mask layer. An etching resistivity of the hard mask layer may be inversely proportional to a difference between a first lateral dimension of the first hole portion and a second lateral dimension of the second hole portion, and the first lateral dimension may be less than the second lateral dimension. The method may also include forming the hard mask layer over the stack structure, and patterning the hard mask layer to form a first patterned hard mask layer that has a first mask opening. The first mask opening may have the first lateral dimension.
    Type: Grant
    Filed: November 21, 2020
    Date of Patent: January 16, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Gang Yang, Xiang Hui Zhao, Biao Zheng, Zui Xin Zeng, Lianjuan Ren, Jian Dai
  • Patent number: 11817348
    Abstract: Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method includes forming a first etch mask over a stack structure, and removing a portion of the stack structure exposed by the first etch mask. The first etch mask may have a first mask opening with a first lateral dimension. The method may also include forming a second etch mask from the first etch mask. The second etch mask may have a second mask opening with a second lateral dimension that is greater than the first lateral dimension. The method may further include removing another portion of the stack structure exposed by the second etch mask to form the hole structure having a first hole portion and a second hole portion connected to and over the first hole portion.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: November 14, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Gang Yang, Xiang Hui Zhao, Biao Zheng, Zui Xin Zeng, Lianjuan Ren, Jian Dai
  • Publication number: 20210104429
    Abstract: Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method for forming a hole structure having a first hole portion and a second hole portion connected to and over the first portion in a stack structure of a semiconductor device includes determining a hard mask layer. An etching resistivity of the hard mask layer may be inversely proportional to a difference between a first lateral dimension of the first hole portion and a second lateral dimension of the second hole portion, and the first lateral dimension may be less than the second lateral dimension. The method may also include forming the hard mask layer over the stack structure, and patterning the hard mask layer to form a first patterned hard mask layer that has a first mask opening. The first mask opening may have the first lateral dimension.
    Type: Application
    Filed: November 21, 2020
    Publication date: April 8, 2021
    Inventors: Gang Yang, Xiang Hui Zhao, Biao Zheng, Zui Xin Zeng, Lianjuan Ren, Jian Dai
  • Publication number: 20200411538
    Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack on a substrate, forming a plurality of staircase regions where each staircase region has a staircase structure having a first number (M) of steps in a first direction; forming a first mask stack to expose a plurality of the staircase regions; removing (M) of the layer stacks in the exposed staircase regions; forming a second mask stack over the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repetitively, sequentially, removing a portion of (2M) of layer stacks and trimming the second mask stack.
    Type: Application
    Filed: August 27, 2020
    Publication date: December 31, 2020
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiang Hui ZHAO, Zui Xin ZENG, Jun HU, Shi ZHANG, Baoyou CHEN
  • Patent number: 10790295
    Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack on a substrate, forming a plurality of staircase regions where each staircase region has a staircase structure having a first number (M) of steps in a first direction; forming a first mask stack to expose a plurality of the staircase regions; removing (M) of the layer stacks in the exposed staircase regions; forming a second mask stack over the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repetitively, sequentially, removing a portion of (2M) of layer stacks and trimming the second mask stack.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: September 29, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiang Hui Zhao, Zui Xin Zeng, Jun Hu, Shi Zhang, Baoyou Chen
  • Publication number: 20200243373
    Abstract: Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method includes forming a first etch mask over a stack structure, and removing a portion of the stack structure exposed by the first etch mask. The first etch mask may have a first mask opening with a first lateral dimension. The method may also include forming a second etch mask from the first etch mask. The second etch mask may have a second mask opening with a second lateral dimension that is greater than the first lateral dimension. The method may further include removing another portion of the stack structure exposed by the second etch mask to form the hole structure having a first hole portion and a second hole portion connected to and over the first hole portion.
    Type: Application
    Filed: March 15, 2019
    Publication date: July 30, 2020
    Inventors: Gang Yang, Xiang Hui Zhao, Biao Zheng, Zui Xin Zeng, Lianjuan Ren, Jian Dai
  • Publication number: 20190355738
    Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack on a substrate, forming a plurality of staircase regions where each staircase region has a staircase structure having a first number (M) of steps in a first direction; forming a first mask stack to expose a plurality of the staircase regions; removing (M) of the layer stacks in the exposed staircase regions; forming a second mask stack over the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repetitively, sequentially, removing a portion of (2M) of layer stacks and trimming the second mask stack.
    Type: Application
    Filed: July 26, 2018
    Publication date: November 21, 2019
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiang Hui ZHAO, Zui Xin ZENG, Jun HU, Shi ZHANG, Baoyou CHEN