Abstract: The present invention related to a crystalline form of compound 3-((L-valyl)amino)-1-propanesulfonic acid, preparation method and uses thereof.

Abstract: A secondary battery includes a positive electrode plate and an electrolyte solution. The electrolyte solution includes a compound having sulfur-oxygen double bond and a nitrile compound. Based on a total mass of the electrolyte solution, a mass percentage of the compound having sulfur-oxygen double bond is A1 %, a mass percentage of the nitrile compound is A2%, 0.08?A1/A2?2.15; and a sum of the mass percentages of the compound having sulfur-oxygen double bond and the nitrile compound is A %, 3?A?15. The positive electrode plate includes a positive electrode material layer, a thickness of the positive electrode material layer is D ?m, and 0.08?A/D?0.42.

Abstract: The present invention discloses a mobile energy storage internet system. The mobile energy storage internet system comprises distributed energy harvesting devices, mobile cold storage/heat storage devices, an energy system dispatching and monitoring center, and cold supply/heat supply terminals. The distributed energy harvesting devices are used for harvesting industrial waste cold energy/heat energy. The energy system dispatching and monitoring center is used for monitoring the residual energy of the distributed energy harvesting devices and the energy demand of the cold supply/heat supply terminals respectively, and mobilizing the mobile cold storage/heat storage devices to the distributed energy harvesting devices to store residual energy or to the cold supply/heat supply terminals to release the stored residual energy.

Abstract: An array substrate, a display panel, a display device, and a method for manufacturing an array substrate are provided. The array substrate includes an array substrate; a plurality of data signal lines arranged on the base substrate; a plurality of fan-out lines arranged side-by-side on the base substrate and respectively lapped with the plurality of data signal lines through adapter holes; and a first test lead wire arranged on the base substrate, wherein the first test lead wire includes a first test pad, a first lead wire segment, and a second lead wire segment, the first lead wire segment is electrically connected to at least a part of the plurality of fan-out lines and arranged in a same layer as the fan-out lines, and the second lead wire segment is electrically connected to the first test pad and lapped with the first lead wire segment through an adapter hole.

Abstract: A power converter includes an input circuit, a conversion circuit, an output circuit and a processor. The input circuit is configured to receive and detect a front stage power from a front stage device. The conversion circuit is coupled to the input circuit. The output circuit is coupled to the conversion circuit and configured to supply power to a back stage device. The processor is coupled to the input circuit, the conversion circuit and the output circuit. The processor is configured to determine whether the front stage power is stable, and is configured to handshake with the back stage device to confirm a conversion power agreed by the back stage device. The processor is further configured to control the conversion circuit to operate at the conversion power, so as to generate an output power to the back stage device.

Abstract: Provided are a recombinant adeno-associated virus (rAAV) genome and a single-polarity rAAV (spAAV) vector formed by packaging same. Specifically, provided is an spAAV genome before packaging, two ends of which are both linear open terminuses, wherein one end does not have an inverted terminal repeat (ITR) or a part thereof, and the other end has a truncated ITR (ITRT), and the ITRT does not form a T-shaped hairpin palindromic structure. The spAAV genome is a single-polarity single-stranded DNA. Also provided are an spAAV vector, a method for delivering an exogenous nucleic acid to a cell by using the vector, and a use of the vector in the preparation of a product for gene expression, gene therapy, gene editing or gene regulation.

Abstract: A tissue suturing device includes a body and a plurality of suture needles. The body includes a guide segment and a tube segment. The guide segment contains a suture needle channel. The tube segment has an accommodating cavity communicated with the suture needle channel. Each of the suture needles includes a main needle segment and a puncture needle segment connected with and spaced apart from the main needle segment. Two of the suture needles, together, connect a suture thread releasably between the puncture needle segments of the two suture needles. The main needle segments are arranged in the suture needle channel. The puncture needle segments carry the suture thread and are located in the accommodating cavity. Each of the suture needles moves along the suture needle channel such that the puncture needle segment returns to the accommodating cavity alone after passing with the suture thread through a tissue wall.

Abstract: Provided in the present invention is a method for preparing chiral alkyl compounds by the asymmetric hydrogenation reaction of iron complex catalysts catalysing olefins: using the disubstituted olefin shown in formula I as a raw material, atmospheric hydrogen as a hydrogen source, FeX2-8-OIQ complex as a catalyst, and a silane compound and acetonitrile as cocatalysts, and reacting for 12-24 hours under the action of a reducing agent to prepare the chiral alkyl compound shown in formula II. The method of the present invention has mild reaction conditions, simple operation, and high atom economy. In addition, the reaction does not require the addition of any other toxic transition metal (such as ruthenium, rhodium, and palladium), and has great practical application value in the synthesis of drugs and materials. The conversion rate of the reaction is also good, generally reaching >99%, and the enantioselectivity is also high, generally 70-99%.

Abstract: Coding including dynamic range handling of high dimensional inverse autocorrelation in optical flow refinement includes obtaining a refinement model from available warped refinement models, wherein the available warped refinement models include a four-parameter scaling refinement model, a three-parameter scaling refinement model, and a four-parameter rotational refinement model, obtaining refined motion vectors using the warped refinement model and previously obtained reference frame data in the absence of data expressly indicating the refined motion vectors in the encoded bitstream, wherein obtaining the refined motion vectors includes using a dynamic range adjusted autocorrelation matrix, generating refined prediction block data using the refined motion vectors, generating reconstructed block data using the refined prediction block data, including the reconstructed block data in reconstructed frame data for the current frame, and outputting the reconstructed frame data.

Abstract: In accordance with embodiments of the present disclosure, a device may include a pulsed emission electronic display having multiple display pixels in order to display an image frame. The display may pulse one or more display pixels of over a plurality of sub-frames within the image frame based on display image data. The device may also include image processing circuitry to generate the display image data based on source image data indicative of an image to be displayed during the image frame. Additionally, the image processing circuitry may dither an order of the plurality of sub-frames.

Abstract: A flip-flop includes a first input circuit, a first NOR logic gate, a stacked gate circuit, a first NAND logic gate and an output circuit. The first input circuit generates a first signal responsive to at least a first data signal, a first or a second clock signal. The first NOR logic gate is coupled between a first and a second node, and generates a second signal responsive to the first signal and a first reset signal. The stacked gate circuit is coupled between the first and a third node, and generates a third signal responsive to the first signal. The first NAND logic gate is coupled between the third and a fourth node, and generates a fourth signal responsive to the third signal and a second reset signal. The output circuit is coupled to the fourth node, and generates a first output signal responsive to the fourth signal.

Abstract: Local passive matrix displays and methods of operation are described. In an embodiment, the display includes a pixel driver chip coupled with a matrix of rows and columns of LEDs. The pixel driver chips may be arranged in rows across the display with separate portions to operate separate matrices of LEDs.

Abstract: A flip-flop includes a first input circuit, a first NAND logic gate, a first stacked gate circuit, a first NOR logic gate, a first output circuit and a first set buffer circuit. The first input circuit is coupled to a first node. The first NAND logic gate is coupled between the first and second node. The first stacked gate circuit is coupled between the first and third node, and configured to generate a third signal responsive to the first signal. The first NOR logic gate is coupled between the third node and a fourth node. The first output circuit is coupled to the fourth node. The first set buffer circuit is coupled to the first NOR logic gate.

Abstract: Hybrid architectures and method methods of operating a display panel are described. In an embodiment, row driver and pixel driver functions are combined in a group of backbone hybrid pixel driver chips, wherein global signal lines are distributed to the backbone hybrid pixel driver chips, where the global signals are manipulated and distributed to a row of pixel driver chips.

Abstract: A flip-flop includes a first input circuit, a first NOR logic gate, a stacked gate circuit, a first NAND logic gate and an output circuit. The first input circuit generates a first signal responsive to at least a first data signal, a first or a second clock signal. The first NOR logic gate is coupled between a first and a second node, and generates a second signal responsive to the first signal and a first reset signal. The stacked gate circuit is coupled between the first and a third node, and generates a third signal responsive to the first signal. The first NAND logic gate is coupled between the third and a fourth node, and generates a fourth signal responsive to the third signal and a second reset signal. The output circuit is coupled to the fourth node, and generates a first output signal responsive to the fourth signal.

Abstract: An optical assembly for a head-up display on a projection surface includes an imaging device, which includes at least one imaging unit, and at least one wavefront manipulator arranged in a beam path between the imaging device and the projection surface. The optical assembly is configured to generate virtual depictions in at least two different image planes, wherein the imaging device has at least a first region and a second region, wherein the imaging device and the wavefront manipulator are configured, in combination, to generate virtual depictions in a first image plane out of images generated in the first region of the imaging device and to generate virtual depictions in a second image plane out of images generated in the second region of the imaging device.

Abstract: Electronic devices, displays, and methods are provided for operating an electronic display in coexistence with sensors that could be adversely impacted by the operation of the electronic display. An electronic device may include an electronic display and a sensor. The electronic display may display image content by light emission during an emission period and periodically enter a quiet period in which the light emission of the electronic display is turned off. The sensor may perform sensing operations during the quiet period without interference from the operation of the electronic display.

Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.

Abstract: Test structures and methods of testing pixel driver chip donor wafers are described. In an embodiment, a redistribution layer is formed over a pixel driver chip donor wafer and probed to determine known good dies, followed by removal of the RDL. In other embodiments, test routing is formed in the pixel driver chip using a polycide material or doped region in the semiconductor wafer.

Abstract: A data processing method includes: generating a service serial number for a target service according to a preset naming rule; obtaining service data of the target service; obtaining a target data table from a plurality of pre-configured data tables, according to the service serial number; and storing the service data to the target data table.