Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.

Abstract: In accordance with embodiments of the present disclosure, a device may include a pulsed emission electronic display having multiple display pixels in order to display an image frame. The display may pulse one or more display pixels of over a plurality of sub-frames within the image frame based on display image data. The device may also include image processing circuitry to generate the display image data based on source image data indicative of an image to be displayed during the image frame. Additionally, the image processing circuitry may dither an order of the plurality of sub-frames.

Abstract: A flip-flop includes a first input circuit, a first NOR logic gate, a stacked gate circuit, a first NAND logic gate and an output circuit. The first input circuit generates a first signal responsive to at least a first data signal, a first or a second clock signal. The first NOR logic gate is coupled between a first and a second node, and generates a second signal responsive to the first signal and a first reset signal. The stacked gate circuit is coupled between the first and a third node, and generates a third signal responsive to the first signal. The first NAND logic gate is coupled between the third and a fourth node, and generates a fourth signal responsive to the third signal and a second reset signal. The output circuit is coupled to the fourth node, and generates a first output signal responsive to the fourth signal.

Abstract: Local passive matrix displays and methods of operation are described. In an embodiment, the display includes a pixel driver chip coupled with a matrix of rows and columns of LEDs. The pixel driver chips may be arranged in rows across the display with separate portions to operate separate matrices of LEDs.

Abstract: A flip-flop includes a first input circuit, a first NAND logic gate, a first stacked gate circuit, a first NOR logic gate, a first output circuit and a first set buffer circuit. The first input circuit is coupled to a first node. The first NAND logic gate is coupled between the first and second node. The first stacked gate circuit is coupled between the first and third node, and configured to generate a third signal responsive to the first signal. The first NOR logic gate is coupled between the third node and a fourth node. The first output circuit is coupled to the fourth node. The first set buffer circuit is coupled to the first NOR logic gate.

Abstract: Hybrid architectures and method methods of operating a display panel are described. In an embodiment, row driver and pixel driver functions are combined in a group of backbone hybrid pixel driver chips, wherein global signal lines are distributed to the backbone hybrid pixel driver chips, where the global signals are manipulated and distributed to a row of pixel driver chips.

Abstract: A flip-flop includes a first input circuit, a first NOR logic gate, a stacked gate circuit, a first NAND logic gate and an output circuit. The first input circuit generates a first signal responsive to at least a first data signal, a first or a second clock signal. The first NOR logic gate is coupled between a first and a second node, and generates a second signal responsive to the first signal and a first reset signal. The stacked gate circuit is coupled between the first and a third node, and generates a third signal responsive to the first signal. The first NAND logic gate is coupled between the third and a fourth node, and generates a fourth signal responsive to the third signal and a second reset signal. The output circuit is coupled to the fourth node, and generates a first output signal responsive to the fourth signal.

Abstract: An optical assembly for a head-up display on a projection surface includes an imaging device, which includes at least one imaging unit, and at least one wavefront manipulator arranged in a beam path between the imaging device and the projection surface. The optical assembly is configured to generate virtual depictions in at least two different image planes, wherein the imaging device has at least a first region and a second region, wherein the imaging device and the wavefront manipulator are configured, in combination, to generate virtual depictions in a first image plane out of images generated in the first region of the imaging device and to generate virtual depictions in a second image plane out of images generated in the second region of the imaging device.

Abstract: Test structures and methods of testing pixel driver chip donor wafers are described. In an embodiment, a redistribution layer is formed over a pixel driver chip donor wafer and probed to determine known good dies, followed by removal of the RDL. In other embodiments, test routing is formed in the pixel driver chip using a polycide material or doped region in the semiconductor wafer.

Abstract: Electronic devices, displays, and methods are provided for operating an electronic display in coexistence with sensors that could be adversely impacted by the operation of the electronic display. An electronic device may include an electronic display and a sensor. The electronic display may display image content by light emission during an emission period and periodically enter a quiet period in which the light emission of the electronic display is turned off. The sensor may perform sensing operations during the quiet period without interference from the operation of the electronic display.

Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.

Abstract: A data processing method includes: generating a service serial number for a target service according to a preset naming rule; obtaining service data of the target service; obtaining a target data table from a plurality of pre-configured data tables, according to the service serial number; and storing the service data to the target data table.

Abstract: A method for compensating a signal of a motor includes acquiring an original signal and nonlinear parameters of the motor; calculating a compensation signal for the original signal according to the acquired nonlinear parameters; and loading the calculated compensation signal into the motor to excite the motor to vibrate. An electronic apparatus and a storage medium are also provided. In this method, the original excitation signal is compensated for nonlinearity according to the nonlinear motor parameters, and is then used for exciting the motor. Therefore, the actual vibration effect can be closer to the expected effect as designed, which can bring more desirable tactility experience.

Abstract: Electronic devices, displays, and methods are provided for performing row shuffling to reduce an appearance of image artifacts during eye movements such as saccades. An electronic display may include a number of rows of display pixels and driving circuitry to drive the rows of pixels. The driving circuitry may spatially shuffle or temporally shuffle, or both spatially and temporally shuffle, a row order of driving the rows of display pixels.

Abstract: Hybrid architectures and method methods of operating a display panel are described. In an embodiment, row driver and pixel driver functions are combined in a group of backbone hybrid pixel driver chips, wherein global signal lines are distributed to the backbone hybrid pixel driver chips, where the global signals are manipulated and distributed to a row of pixel driver chips.

Abstract: In accordance with embodiments of the present disclosure, a device may include a pulsed emission electronic display having multiple display pixels in order to display an image frame. The display may pulse one or more display pixels of over a plurality of sub-frames within the image frame based on display image data. The device may also include image processing circuitry to generate the display image data based on source image data indicative of an image to be displayed during the image frame. Additionally, the image processing circuitry may dither an order of the plurality of sub-frames.

Abstract: Touch sensitive display technologies (e.g., integrated touch-display pixel-based systems) are evolving to contain more analog and digital circuits inside the panel itself instead of the traditionally simple thin-film transistors. This improves the display characteristics but makes those circuits more vulnerable to the impact of external ESD strikes, which can degrade the user experience. This disclosure describes a series of circuits and techniques to mitigate the impact of these discharges on front of screen artifacts and potential false touches. These circuits and techniques may include: performing configuration-only panel updates independently of the image refresh rate, improving the in-panel memory circuits to make them resistant to unexpected pin toggles via disabling of a write path in response to a read clock, implementing a pin corruption detector and implementing a supply injection detector.

Abstract: An electronic device may include an electronic display including display pixels to display an image based on compensated image data. As image data is written to a pixel in the row of pixels, capacitive coupling at a driver may lead to distortion on the driver. In particular, the capacitive coupling may cause distortion at a storage capacitor, which may lead to current droop at the pixel. The current droop may be reduced or eliminated in each pixel by performing pixel compensation. The pattern of the pixel compensation may be selected such that, over a number of subframes, an average amount of light is the same or similar to what would be emitted had pixel compensation been performed on each pixel in each subframe.

Abstract: A device includes a servo controller that includes or that is coupled to memory. The memory stores multiple distinct disturbance control schemes. The servo controller is configured to select and implement one of the disturbance control schemes in response to receiving a command from a host. The servo controller can be implemented on a system on a chip.

Abstract: Local passive matrix displays and methods of operation are described. In an embodiment, the display includes a pixel driver chip coupled with a matrix of rows and columns of LEDs. The pixel driver chips may be arranged in rows across the display with separate portions to operate separate matrices of LEDs.