Patents by Inventor Xiang-Rui Chang

Xiang-Rui Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11836321
    Abstract: An optical sensing device includes a substrate, sensing elements, a planarization layer, and a light-shielding layer. The sensing elements are located on the substrate. Each sensing element includes a first net-shaped electrode, a second net-shaped electrode, and a sensing layer. The first net-shaped electrode is located between the sensing layer and the substrate. The sensing layer is located between the first net-shaped electrode and the second net-shaped electrode. The planarization layer is located on the sensing elements and the substrate and has via holes. The light-shielding layer is located on the planarization layer and includes net-shaped light-shielding patterns. The net-shaped light-shielding patterns are overlapped with the second net-shaped electrodes of the sensing elements, respectively, and the net-shaped light-shielding patterns are electrically connected to the second net-shaped electrodes of the sensing elements via the via holes, respectively.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: December 5, 2023
    Assignee: AUO Corporation
    Inventors: Xiang-Rui Chang, Chao-Chien Chiu
  • Publication number: 20230026218
    Abstract: An optical sensing device includes a substrate, sensing elements, a planarization layer, and a light-shielding layer. The sensing elements are located on the substrate. Each sensing element includes a first net-shaped electrode, a second net-shaped electrode, and a sensing layer. The first net-shaped electrode is located between the sensing layer and the substrate. The sensing layer is located between the first net-shaped electrode and the second net-shaped electrode. The planarization layer is located on the sensing elements and the substrate and has via holes. The light-shielding layer is located on the planarization layer and includes net-shaped light-shielding patterns. The net-shaped light-shielding patterns are overlapped with the second net-shaped electrodes of the sensing elements, respectively, and the net-shaped light-shielding patterns are electrically connected to the second net-shaped electrodes of the sensing elements via the via holes, respectively.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 26, 2023
    Applicant: AUO Corporation
    Inventors: Xiang-Rui Chang, Chao-Chien Chiu
  • Patent number: 10505052
    Abstract: A semiconductor device includes a first film disposed over a semiconductor substrate, the first film comprising a first transition metal dichalcogenide; a second film disposed over the first film, the second film comprising a second transition metal dichalcogenide different from the first transition metal dichalcogenide; source and drain features formed over the second film; a first gate stack formed over the second film and interposed between the source and drain features; and a second gate stack formed over the semiconductor substrate opposite from the first gate stack such that the semiconductor substrate is between the first and second gate stacks.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 10, 2019
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Shih-Yen Lin, Chi-Wen Liu, Chong-Rong Wu, Xiang-Rui Chang
  • Publication number: 20190123211
    Abstract: A semiconductor device includes a first film disposed over a semiconductor substrate, the first film comprising a first transition metal dichalcogenide; a second film disposed over the first film, the second film comprising a second transition metal dichalcogenide different from the first transition metal dichalcogenide; source and drain features formed over the second film; a first gate stack formed over the second film and interposed between the source and drain features; and a second gate stack formed over the semiconductor substrate opposite from the first gate stack such that the semiconductor substrate is between the first and second gate stacks.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Shih-Yen Lin, Chi-Wen Liu, Chong-Rong Wu, Xiang-Rui Chang
  • Patent number: 10164122
    Abstract: A method includes depositing a first transition metal film having a first transition metal on a substrate and performing a first sulfurization process to the first transition metal film, thereby forming a first transition metal sulfide film. The method further includes depositing a second transition metal film having a second transition metal on the first transition metal sulfide film and performing a second sulfurization process to the second transition metal film, thereby forming a second transition metal sulfide film. The first and the second transition metals are different. The method further includes forming a gate stack, and source and drain features over the second transition metal sulfide film. The gate stack is interposed between the source and drain features. The gate stack, source and drain features, the first transition metal sulfide film and the second transition metal sulfide film are configured to function as a hetero-structure transistor.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yen Lin, Chi-Wen Liu, Chong-Rong Wu, Xiang-Rui Chang
  • Publication number: 20180151752
    Abstract: A method includes depositing a first transition metal film having a first transition metal on a substrate and performing a first sulfurization process to the first transition metal film, thereby forming a first transition metal sulfide film. The method further includes depositing a second transition metal film having a second transition metal on the first transition metal sulfide film and performing a second sulfurization process to the second transition metal film, thereby forming a second transition metal sulfide film. The first and the second transition metals are different. The method further includes forming a gate stack, and source and drain features over the second transition metal sulfide film. The gate stack is interposed between the source and drain features. The gate stack, source and drain features, the first transition metal sulfide film and the second transition metal sulfide film are configured to function as a hetero-structure transistor.
    Type: Application
    Filed: January 31, 2018
    Publication date: May 31, 2018
    Inventors: Shih-Yen Lin, Chi-Wen Liu, Chong-Rong Wu, Xiang-Rui Chang