Abstract: A silicone rubber with UV aging resistance and low water absorption and its preparation method and application are provided. The preparation method uses a coupling agent KH570 and glyceryl monostearate to perform modified treatment on titanium dioxide to obtain modified titanium dioxide, uses a surface-modified coupling agent A171 and glyceryl monostearate to perform modified treatment on fumed silica to obtain modified fumed silica, and further performs subsequent treatment on methyl vinyl siloxane raw rubber, silicone oil, aluminum hydroxide, the modified fumed silica, the modified titanium dioxide, zinc oxide, ?-alumina, a coupling agent KH560, a defoamer, iron oxide and a vulcanizing agent to obtain the silicone rubber. The silicone rubber prepared by the preparation method has low water absorption and excellent aging resistance, and its mechanical and electrical properties are also superior.

Abstract: A test method of wheel speed simulation and acquisition equipment for an EPB rear wheel anti-lock brake test is provided. The equipment includes a master computer, wheel simulation sets and an EPB system with a wheel anti-lock brake function, where the master computer includes a motor rotating speed control module, an EPB-required signal simulation module and a target wheel speed calculation module; the wheel simulation sets include motor drivers, motors, gears and wheel speed sensors; outputs of the wheel speed sensors are connected into the EPB system; the motor rotating speed control module is connected with the motor drivers; the EPB system to be tested includes EPB calipers, pressure sensors are arranged in the EPB calipers; the target wheel speed calculation module calculates a target wheel speed and sends the target wheel speed to the motor rotating speed control module to complete the control of an actual wheel speed.

Abstract: The present disclosure relates to a display device and a method of manufacturing the same. The display device includes: a plurality of display units, each display unit including one or more pixels; and a plurality of elastically stretchable stretching units respectively connected among the plurality of display units and forming elastic connection points with the display units, the stretching units and the plurality of display units forming a net-shaped distribution structure, wherein in a state that the display device is not under tension, a connection lines between the elastic connection points at both ends of the stretching unit are not parallel to a normal of the display units connected with at least one end of the stretching unit at the elastic connection points.

Abstract: The present disclosure discloses a self-adaptive trigger acquisition method of an airborne bathymetric survey laser radar, including calculating a distance between laser light and a water surface and a height between the laser radar and the water surface, and obtaining delay time before sampling; converting water surface and water bottom echo numerical values into corresponding voltage amplitude values, then calculating corresponding electric signals, and calculating light energy by a photoelectric conversion relation; determining a water body attenuation coefficient by water surface and water bottom light energy losses; and determining a maximum water depth by the solved water body attenuation coefficient, then solving sampling time, and finally realizing self-adaptive trigger acquisition.

Abstract: A display panel comprises a display portion comprising sub-pixel rows and a gate driver circuit comprising gate driver units in cascade. Each sub-pixel row comprises sub-pixel units, and a pixel circuit comprising a switching transistor, a first reset transistor and a second reset transistor is provided in each sub-pixel unit. Each gate driver unit comprises first and second signal output terminals. Agate of the switching transistor in a b-th row is connected to the second signal output terminal of the gate driver unit at an a-th stage, a gate of the first reset transistor in the b-th row is connected to the first signal output terminal of the gate driver unit at a b-th stage, and a gate of the second reset transistor in the b-th row is connected to the first signal output terminal of the gate driver unit at a c-th stage.

Abstract: A surface cleaning head may include a fluid distributor configured to distribute a cleaning fluid, an agitator configured to absorb at least a portion of the distributed cleaning fluid and to agitate debris on the surface to be cleaned, a fluid stripper configured to remove, from the agitator, at least a portion of the distributed cleaning fluid absorbed by the agitator, a debris container, and a removable cover. The debris container may include a solid debris chamber and a fluid debris chamber. The removable cover may include a fluid catch plate configured to transfer at least a portion of the cleaning fluid removed from the agitator by the fluid stripper to the fluid debris chamber, the fluid catch plate being configured to selectively transition between an in-use position and a cleaning position when the removable cover is removed from the surface cleaning head.

Abstract: A display panel comprises a display portion comprising sub-pixel rows and a gate driver circuit comprising gate driver units in cascade. Each sub-pixel row comprises sub-pixel units, and a pixel circuit comprising a switching transistor, a first reset transistor and a second reset transistor is provided in each sub-pixel unit. Each gate driver unit comprises first and second signal output terminals. A gate of the switching transistor in a b-th row is connected to the second signal output terminal of the gate driver unit at an a-th stage, a gate of the first reset transistor in the b-th row is connected to the first signal output terminal of the gate driver unit at a b-th stage, and a gate of the second reset transistor in the b-th row is connected to the first signal output terminal of the gate driver unit at a c-th stage.

Abstract: The present application discloses a planar High-Electron-Mobility Transistor (HEMT), which includes a hetero-junction consisting of a first semiconductor epitaxial layer and a second semiconductor epitaxial layer, and two-dimensional electron gas located at an interface of the hetero-junction; a bottom surface of a gate trench of a trench gate is located at a bottom of the two-dimensional electron gas to cut off the two-dimensional electron gas; when gate-source voltage is higher than or equal to threshold voltage, an inversion layer is formed on a surface of the first semiconductor epitaxial layer covered by side surfaces and a bottom surface of a gate conductive material layer, and the source-end and drain-end two-dimensional electron gas is conducted to enable the device to be on; when the gate-source voltage is lower than the threshold voltage, the source-end and drain-end two-dimensional electron gas is cut off to enable the device to be off.

Abstract: A surface cleaning head may include a fluid distributor configured to distribute a cleaning fluid, an agitator configured to absorb at least a portion of the distributed cleaning fluid and to agitate debris on the surface to be cleaned, a fluid stripper configured to remove, from the agitator, at least a portion of the distributed cleaning fluid absorbed by the agitator, a debris container, and a removable cover. The debris container may include a solid debris chamber and a fluid debris chamber. The removable cover may include a fluid catch plate configured to transfer at least a portion of the cleaning fluid removed from the agitator by the fluid stripper to the fluid debris chamber, the fluid catch plate being configured to selectively transition between an in-use position and a cleaning position when the removable cover is removed from the surface cleaning head.

Abstract: A gate driving circuit includes gate driving units. Each of the gate driving units includes a node voltage control module and a pull-down module. The node voltage control module includes a first module and a storage module. The first module outputs a first voltage signal at a first node in response to a pull-down control signal at a first control port. The storage module includes a first port receiving the first voltage signal, and a second terminal electrically connected to the first node. The pull-down module outputs a first working signal for controlling a plurality of sub-pixels to turn off at an output port of the gate driving unit in response to the first voltage signal. The storage module maintains the first voltage signal applied on the first node to maintain the first working signal at the output port of the gate driving unit controlled by the pull-down module.

Abstract: A gate driving circuit includes a gate driving unit arranged in a multi-stage cascade. The gate driving unit includes a pull-up control module, a pull-up node, a first output module, a second output module, a pull-down control module, a first pull-down module, a pull-down node, a second pull-down module, and a pull-down maintenance module. The pull-up control module is configured to pull up a potential of the pull-up node under a control of a first clock signal input at a first clock signal input terminal. The pull-down control module is configured to pull up a potential of the pull-down node under a control of the first clock signal. The first pull-down module is configured to pull the potential of the pull-down node down to a potential of the first clock signal under a control of the potential of the pull-up node.

Abstract: A gate driving circuit includes gate driving units. Each of the gate driving units includes a node voltage control module and a pull-down module. The node voltage control module includes a first module and a storage module. The first module outputs a first voltage signal at a first node in response to a pull-down control signal at a first control port. The storage module includes a first port receiving the first voltage signal, and a second terminal electrically connected to the first node. The pull-down module outputs a first working signal for controlling a plurality of sub-pixels to turn off at an output port of the gate driving unit in response to the first voltage signal. The storage module maintains the first voltage signal applied on the first node to maintain the first working signal at the output port of the gate driving unit controlled by the pull-down module.

Abstract: A gate driving circuit includes a gate driving unit arranged in a multi-stage cascade. The gate driving unit includes a pull-up control module, a pull-up node, a first output module, a second output module, a pull-down control module, a first pull-down module, a pull-down node, a second pull-down module, and a pull-down maintenance module. The pull-up control module is configured to pull up a potential of the pull-up node under a control of a first clock signal input at a first clock signal input terminal. The pull-down control module is configured to pull up a potential of the pull-down node under a control of the first clock signal. The first pull-down module is configured to pull the potential of the pull-down node down to a potential of the first clock signal under a control of the potential of the pull-up node.

Abstract: Provided herein are GLP-1 receptor modulator compounds, pharmaceutical compositions, methods of their preparation, and methods of their use in treatment, and/or diagnosis.

Abstract: Coherent optical communications technology for recovery of 1D and 2D formatted optical signals. For example, 1D or 2D formatted signals that travel through fiber optic media may be recovered by separating the light into X- and Y-polarization components, rotating one polarization component (e.g., Y-component) into the polarization space of the other component (e.g., Y-component into the X-polarization space), delaying the rotated component enough to avoid destructive interference and combining the delayed component with the undelayed component to form a folded optical signal, which may then be processed as a X-polarized signal.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first transistor region and a second transistor region and then forming a first gate structure on the first transistor region and a second gate structure on the second transistor region, in which the first gate structure includes a first hard mask, the second gate structure includes a second hard mask, and the first hard mask and the second hard mask have different thicknesses. Next, a patterned mask is formed around the first gate structure and the second gate structure, and then part of the first hard mask is removed.

Abstract: The disclosed technology allows for 1+1 optical protection and may improve coherent module output optical power by 3 dB over similar transmitter (Tx) and receiver (Rx) implementation complexity, as well as allow for integration into existing datacenter formats.

Abstract: A receiver system is provided for receiving a coherent Pulse Amplitude Modulation (PAM) encoded signal. The receiver system may include an optical polarization component configured to modulate a polarization of the received coherent PAM encoded signal. The receiver system may further include a digital signal processor (DSP) configured to perform polarization recovery between the received coherent PAM encoded signal and the LO signal using a first control loop, and to perform phase recovery between the received coherent PAM encoded signal and the LO signal using a second control loop.

Abstract: Methods and apparatus for monitoring chirp in a modulated light beam. The modulated light is passed through a variable dispersion element or “VDE”, and the light from the variable dispersion element is detected to yield a signal. A parameter which represents the strength of modulation in the light after passage through the VDE such as the peak intensity of the modulated light is measured as the VDE is controlled to vary the applied dispersion. The chip is determined from the variation of the parameter with dispersion, such as from the dispersions at which the parameter is at minima. The method can be applied to beams modulated by common digital transmitters used in optical communication systems.