Patents by Inventor Xiangang Huang

Xiangang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240168878
    Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to: perform a programming operation on the first group of memory cells of the first erase block; monitor a quantity of programming and/or erase operations performed on the second group of memory cells subsequent to the programming of the first group of memory cells; and perform an action on the first erase block responsive to the quantity of programming and/or erase operations performed on the second group of memory cells meeting a criteria.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 23, 2024
    Inventors: Akira Goda, Kishore K. Muchherla, Shyam Sunder Raghunathan, Leo Raimondo, Jung Sheng Hoei, Xiangang Luo, Ashutosh Malshe, Jianmin Huang
  • Publication number: 20240168879
    Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells each comprising: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is configured to determine a cumulative amount of read disturb stress experienced by the first erase block by monitoring read disturb stress experienced by the first erase block due to: read operations performed on the first erase block; read operations performed on the second erase block; and program verify operations performed on the second erase block. The controller can perform an action on the first erase block responsive to the cumulative amount of read disturb stress experienced by the first erase block meeting a criteria.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 23, 2024
    Inventors: Akira Goda, Kishore K. Muchherla, Shyam Sunder Raghunathan, Leo Raimondo, Jung Sheng Hoei, Xiangang Luo, Ashutosh Malshe, Jianmin Huang
  • Patent number: 11989433
    Abstract: A method includes forming at least a portion of a first superblock using a first subset of blocks from at least one memory die of a memory sub-system and forming at least a portion of a second superblock using a second subset of blocks from the at least one memory die of the memory sub-system.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: May 21, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Jianmin Huang, Xiangang Luo
  • Patent number: 11934268
    Abstract: An example apparatus includes a media management superblock component configured to determine that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks; compare the quantity of bad blocks to a bad block criteria; and write host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria. The use of the superblock with a particular quantity of bad block minimizes yield loss for non-use of partial superblocks.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jianmin Huang, Xiangang Luo, Kulachet Tanpairoj
  • Patent number: 11928356
    Abstract: Methods, systems, and apparatuses related to source address memory management are described. For example, a controller can be coupled to a memory device to select a source block, a destination block, and a metadata block. The controller can store metadata indicative of an address of the source block in the metadata block. The controller can perform a memory management operation to transfer data from the source block to the destination block.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Jianmin Huang, Xiaolai Zhu
  • Publication number: 20240069776
    Abstract: A system can include a memory device with multiple management units, each management unit made up of multiple blocks, and a processing device, operatively coupled with the memory device, to perform various operations including identifying, among the management units, some complete management units and some incomplete management units, as well as performing one type of operation using one or more complete management units. The operations can also include performing another type of operation using one or more incomplete management units where this other type of operation include writing, to one or more incomplete management units, metadata associated with the data stored in complete management units.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 29, 2024
    Inventors: Xiangang Luo, Jianmin Huang, Hong Lu, Kulachet Tanpairoj, Chun Sum Yeung, Jameer Mulani, Nitul Gohain, Uday Bhasker V. Vudugandla
  • Patent number: 11914490
    Abstract: A variety of applications can include apparatus and/or methods to preemptively detect defect prone memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facilitate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Harish Reddy Singidi, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Jianmin Huang, Xiangang Luo, Ashutosh Malshe
  • Patent number: 7792930
    Abstract: A set of network devices having varying device attributes, such as varying attributes due to different operating system versions, different hardware versions, or different hardware platforms, may be efficiently managed. A syntax file may be used to describe constraints relating to attributes of multiple versions of the network devices. At least one device configuration file (DCF) stores version-based differences relating to the different versions of the network devices, the syntax file and at least one the one DCF collectively describe a set of constraints for the attributes of the network devices.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: September 7, 2010
    Assignee: Juniper Networks, Inc.
    Inventors: David Lei Zhang, Brian Yean-Shiang Leu, Chi-Chang Lin, Xiangang Huang, James E. Fehrle