Abstract: An array substrate is provided. The array substrate includes a pixel driving circuit having a first reset transistor and a second reset transistor. At least a portion of a gate electrode of a first reset transistor in a present row of pixel driving circuits and at least a portion of a gate electrode of a second reset transistor in a previous row of pixel driving circuits are parts of a unitary structure. The gate electrode of the first reset transistor in the present row of pixel driving circuits and the gate electrode of the second reset transistor in the previous row of pixel driving circuits are arranged along a direction non-parallel to an extension direction of reset control signal lines.

Abstract: Disclosed are a display substrate and a display apparatus, the display substrate includes a display region and a non-display region, the display substrate includes a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer includes multiple pixel circuits arranged in an array and located in the display region and multiple drive circuits located in the non-display region. At least one pixel circuit includes multiple transistors and the multiple drive circuits are configured to provide drive signals to the multiple transistors; the circuit structure layer further includes: a high-level power supply line and a low-level power supply line located in the non-display region, at least one drive circuit is electrically connected with the high-level power supply line and the low-level power supply line respectively, and the high-level power supply line and the low-level power supply line extend along a first direction.

Abstract: A display substrate and a display device. A sub-pixel in the display substrate comprises: a first initialization signal line and a second initialization signal line, the potentials of initialization signals transmitted by the first initialization signal line and the second initialization signal line being different; a sub-pixel driving circuit in the sub-pixel comprises a drive transistor, a first reset transistor and a second reset transistor; a first electrode of the drive transistor is coupled to a light-emitting element; a first electrode of the first reset transistor is coupled to a gate electrode of the drive transistor, and a second electrode of the first reset transistor is coupled to the first initialization signal line; a first electrode of the second reset transistor is coupled to the light-emitting element, and a second electrode of the second reset transistor is coupled to the second initialization signal line.

Abstract: A display apparatus includes a plurality of first touch channels, second touch channels, first touch traces, second touch traces, and a first touch chip and second touch chip. At least one first touch channel and second touch channel are arranged in each sub-region, and the at least one first touch channel and second touch channel are arranged crosswise and insulated from each other; first touch channels located in different sub-regions are insulated from each other, and second touch channels located in different sub-regions are insulated from each other. In any two sub-regions, first touch traces connected to first touch channels and second touch traces connected to second touch channels are connected to the first touch chip; in remaining two sub-regions except the any two sub-regions, first touch traces connected to first touch channels and second touch traces connected to second touch channels are connected to the second touch chip.

Abstract: A display apparatus includes a plurality of rows of subpixels, a first scan circuit, and a second scan circuit. The first scan circuit includes a plurality of first scan units and a plurality of second scan units alternately arranged. The second scan circuit includes a plurality of third scan units. A respective first scan unit and a respective second scan unit are configured to provide control signals to two adjacent rows of subpixels, respectively. A respective third scan unit is configured to provide control signals to the first adjacent row of subpixels and the second adjacent row of subpixels. Control signals output from the respective first scan unit are out of phase with respect to control signals output from the respective second scan unit. A first duration of an effective voltage of a first control signal output from the respective first scan unit is greater than a second duration of an effective voltage of a second control signal output from the respective second scan unit.

Abstract: A scan circuit is provided. The scan circuit includes a plurality of scan units. A respective scan unit of the plurality of scan units includes a plurality of transistors. A respective gate electrode of a respective transistor of the plurality of transistors includes a first portion and a second portion in different layers. First portions of respective gate electrodes of the plurality of transistors in the respective scan unit are configured to be provided with a power supply signal. Second portions of the respective gate electrodes of the plurality of transistors in the respective scan unit are configured to be provided with gate scanning signals, respectively. First portions of gate electrodes of at least two transistors in the respective scan unit are parts of a unitary structure.

Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate, a pixel defining layer and at least one photo spacer. The pixel defining layer is disposed on the base substrate and includes a plurality of openings, the at least one photo spacer is disposed on a side of the pixel defining layer away from the base substrate. A distance from any point at a bottom of the at least one photo spacer contacting the pixel defining layer to an upper edge of a side wall of the plurality of openings is greater than or equal to 5 ?m.

Abstract: A display substrate and a display device.

Abstract: A display substrate includes: a base substrate; light-emitting elements located in a display area; pixel driving circuits located respectively connected to the light-emitting elements, each pixel driving circuit including an N-type transistor and a P-type transistor; a first gate driving circuit, a second gate driving circuit and a third gate driving circuit in a border area of the display area, the first and third gate driving circuits being connected with the P-type transistor, the second gate driving circuit being connected with the N-type transistor, and orthographic projections of the first to third gate driving circuits on the base substrate are not overlapped with each other; and a planarization layer located between the pixel driving circuits and the light-emitting elements.

Abstract: An anti-corrosion circuit, an array substrate and an electronic device are provided. The array substrate includes: source signal lines, provided in the display area, extending along a first direction and arranged sequentially along a second direction; a first power bus line, provided in the peripheral area and including a main body portion extending along the second direction; an electrostatic discharge protection circuit, provided on a side of the main body portion away from the display area and electrically connected to the source signal lines, and including first sub-signal lines and second sub-signal lines. The first sub-signal lines and the second sub-signal lines extend along the second direction and are alternately arranged along the first direction, and the main body portion is adjacent to one first sub- signal line, and electrical property of the first power bus line is the same as electrical property of the one first sub-signal line.

Abstract: A display substrate, comprising a substrate, a plurality of first circuit groups, at least one group of first connecting lines, and at least one group of second connecting lines. The substrate comprises a display area, and a binding area, which is located on one side of the display area. The plurality of first circuit groups, the at least one group of first connecting lines and the at least one group of second connecting lines are located in the binding area. The plurality of first circuit groups are arranged in a first direction. At least two adjacent first circuit groups-among the plurality of first circuit groups are electrically connected by means of one group of first connecting lines and one group of second connecting lines.

Abstract: An array substrate is provided. The array substrate includes a first semiconductor material layer and a second semiconductor material layer on a side of the first semiconductor material layer away from a base substrate. The first semiconductor material layer includes at least active layers of the driving transistor and the data write transistor. The second semiconductor material layer includes at least an active layer of the compensating transistor. A first capacitance is at least partially formed between a gate connecting pad and at least one of the second semiconductor material layer or a first node connecting line. A second capacitance is formed between the first node connecting line and a respective second gate line. The first capacitance is greater than the second capacitance.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate; a pixel circuit layer, on the base substrate; an anode layer, at a side of the pixel circuit layer away from the base substrate, the pixel circuit layer includes a plurality of pixel driving circuits, the plurality of pixel driving circuits include a first pixel driving circuit, the anode layer includes a plurality of anodes, the plurality of anodes include a first anode, the first anode includes a first main body portion and a first connection portion, and the first connection portion is electrically connected to the first pixel driving circuit, an orthographic projection of the first anode on the base substrate covers one thin film transistor in the first pixel driving circuit.

Abstract: An array substrate includes a substrate, data lines, fan-out leads, first dummy lines an second dummy lines. A fan-out lead includes a first lead and a second lead. The first lead extends from a lead-out region to a first wiring region. An end of the second lead is electrically connected to the first lead, and another end of the second lead is electrically connected to one data line. The first dummy lines are disposed in first wiring regions and located on a side, away from the lead-out region, of all first leads as a whole. A part of the second dummy lines is located in a second wiring region where no second lead is arranged; and another part of the second dummy lines is located in the second wiring region where the second lead is arranged and is located on at least one side of the second lead.

Abstract: A display substrate, includes: a base substrate; light-emitting elements located in a display area; pixel driving circuits located respectively connected to the light-emitting elements, each pixel driving circuit including an N-type transistor and a P-type transistor; a first gate driving circuit, a second gate driving circuit and a third gate driving circuit in a border area of the display area, the first and third gate driving circuits being connected with the P-type transistor, the second gate driving circuit being connected with the N-type transistor, and orthographic projections of the first to third gate driving circuits on the base substrate are not overlapped with each other; orthographic projections of adjacent boundary areas of the first and second gate driving circuits on the base substrate are at least partially nested; and a planarization layer located between the pixel driving circuits and the light-emitting elements.

Abstract: Disclosed are a display substrate and a preparation method therefor, and a display apparatus. The display substrate includes a fanout region, the fanout region includes a first transition region, an isolation dam region, and a second transition region. The fanout region includes a gate metal layer and a source-drain metal layer, the gate metal layer includes any one or more of following: a first gate metal layer, a second gate metal layer, and a third gate metal layer. The gate metal layer is provided with a power supply connection line, the source-drain metal layer is provided with a first power supply line, the first power supply line is disposed in the first transition region and the second transition region, a first power supply line of the first transition region and a first power supply line of the second transition region are interconnected through the power supply connection line.

Abstract: A touch structure, a touch display panel, and a display device are provided. The touch structure includes a substrate and a first metal grid electrode layer, an insulating layer, a second metal grid electrode layer on the substrate. The first metal grid electrode layer is on a side of the second metal grid electrode layer away from the substrate; the first metal grid electrode layer includes a plurality of first metal grids formed by a plurality of first metal lines, the second metal grid electrode layer includes a plurality of second metal grids formed by a plurality of second metal lines, first portions of the plurality of the first metal lines and second portions of the plurality of the second metal lines have same line extension directions, respectively, and overlap with each other in a direction perpendicular to a surface of the substrate.

Abstract: A display panel includes a plurality of pixel driving circuits and a plurality of first data lines that are all disposed in a display area, a plurality of pads disposed in a non-display area, and at least one data lead. The pixel driving circuits constitute a plurality of circuit columns arranged in a first direction. A circuit column includes at least two pixel driving circuits arranged in a second direction. A first data line is coupled to the at least two pixel driving circuits in the circuit column. A data lead in the at least one data lead is coupled to the first data line and at least one pad in the plurality of pads. The circuit columns constitute a plurality of circuit groups arranged in the first direction, and a circuit group includes at least one circuit column. The data lead is disposed between two adjacent circuit groups.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and a plurality of sub-pixels on the base substrate. Each sub-pixel includes a pixel circuit; pixel circuits are in columns in a first direction and rows in a second direction. The sub-pixels include a first sub-pixel, and the display substrate further includes a first data line extended in the first direction and connected with the first sub-pixel. The sub-pixels further include a second sub-pixel directly adjacent to the first sub-pixel in the second direction. A first capacitor electrode in the first sub-pixel and a first capacitor electrode in the second sub-pixel are in a same layer and are spaced apart from each other; and the first capacitor electrode in the first sub-pixel is overlapped with the first data line in a direction perpendicular to the base substrate to provide a first capacitor.

Abstract: An array substrate and a display device are disclosed. The array substrate includes: a base substrate, including a display region and a bonding region located around the display region; a plurality of first pixel driving circuits located on the base substrate; a plurality of first data lines; and a plurality of first leads, the display region includes a first region and a second region located at a side of the first region, and the plurality of first pixel driving circuits are located in the second region, the plurality of first data lines are located in a layer different from a layer where the plurality of first leads are located.