Patents by Inventor Xianggong GUO

Xianggong GUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998885
    Abstract: The present invention provides a method for equivalent high sampling rate FIR filtering based on FPGA, first, the coefficients h(k) of FIR filter are found by using MATLAB, multiplied by an integer and then rounded for the purpose that the rounded coefficients h(k) can be directly used into a FPGA, then the ADC's output of high data rate fs is lowered by dividing the ADC's output x(n) into M parallel data streams xi(n) of low data rate, and the M×L samples in one clock cycle is obtained by delaying the M parallel data streams xi(n) simultaneously by 1, 2, . . . , L? periods of the synchronous clock, at last, the samples yi(n) of FIR filtering output is calculated according to the samples selected from the M×L samples, and the filtered data y(n) of data rate fs is obtained by putting the samples yi(n) together in ascending order of i. Thus, the continuous FIR filtering of an ADC's output sampled with high sampling rate is realized, while the data rates before and after the FIR filtering are unchanged.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: May 4, 2021
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Lianping Guo, Hao Zeng, Feng Tan, Duyu Qiu, Xianggong Guo, Yu Li
  • Publication number: 20190080035
    Abstract: The present invention provides a method for equivalent high sampling rate FIR filtering based on FPGA, first, the coefficients h(k) of FIR filter are found by using MATLAB, multiplied by an integer and then rounded for the purpose that the rounded coefficients h(k) can be directly used into a FPGA, then the ADC's output of high data rate fs is lowered by dividing the ADC's output x(n) into M parallel data streams xi(n) of low data rate, and the M×L samples in one clock circle is obtained by delaying the M parallel data streams xi(n) simultaneously by 1, 2, . . . , L? periods of the synchronous clock, at last, the samples yi(n) of FIR filtering output is calculated according to the samples selected from the M×L samples, and the filtered data y(n) of data rate fs is obtained by putting the samples yi(n) together in ascending order of i. Thus, the continuous FIR filtering of an ADC's output sampled with high sampling rate is realized, while the data rates before and after the FIR filtering are unchanged.
    Type: Application
    Filed: October 18, 2018
    Publication date: March 14, 2019
    Applicant: University of Electronic Science and Technology of China
    Inventors: Lianping GUO, Hao ZENG, Feng TAN, Duyu QIU, Xianggong GUO, Yu LI