Patents by Inventor Xiangguo Meng

Xiangguo Meng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961740
    Abstract: The present application discloses a method for manufacturing semiconductor devices having gate dielectric layers at different thickness. The gate dielectric layers having other than the minimum thickness are respectively formed by the following steps: step 1: forming a first mask layer; step 2: etching the first mask layer to form a first opening; step 3: etching a semiconductor substrate at the bottom of the first opening to form a second groove; step 4: filling the second groove and the first opening with the second material layer; step 5: etching back the second material layer to form the gate dielectric layer, such that the second material layer is flush with the top surface of the semiconductor substrate; and step 6: removing the first mask layer.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: April 16, 2024
    Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION
    Inventors: Lian Lu, Yizheng Zhu, Xiangguo Meng
  • Publication number: 20220139711
    Abstract: The present application discloses a method for manufacturing semiconductor devices having gate dielectric layers at different thickness. The gate dielectric layers having other than the minimum thickness are respectively formed by the following steps: step 1: forming a first mask layer; step 2: etching the first mask layer to form a first opening; step 3: etching a semiconductor substrate at the bottom of the first opening to form a second groove; step 4: filling the second groove and the first opening with the second material layer; step 5: etching back the second material layer to form the gate dielectric layer, such that the second material layer is flush with the top surface of the semiconductor substrate; and step 6: removing the first mask layer.
    Type: Application
    Filed: November 1, 2021
    Publication date: May 5, 2022
    Inventors: Lian LU, Yizheng Zhu, Xiangguo Meng
  • Patent number: 9449866
    Abstract: The invention discloses a treatment process for a semiconductor, comprising providing a substrate, the substrate comprises silicon material; defining a trench region; removing the trench region using a plasma etching process and exposing a trench surface, the trench surface comprising surface defects; forming an oxidation layer overlaying the trench surface; removing the oxidation layer and at least a portion of the surface defects; expositing a treated trench surface, the treated trench surface being substantially free from surface defects; and forming a layer of silicon germanium material overlaying the treated trench surface. The invention further provides a semiconductor processing technique used to eliminate or reduce dislocation defect on the semiconductor device and improve device performance. In the treatment process, a substrate is subjected to at least one oxidation-deoxidation processes, where an oxidation layer is formed and then removed.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: September 20, 2016
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Quanbo Li, Jun Huang, Xiangguo Meng, Yu Zhang
  • Publication number: 20160218005
    Abstract: A process is used to form a protective layer to cover a divot between two regions of a semiconductor material. During etching processes, the protective layer protects the divot to be etched away and reduces material loss of a Silicon (Si)-shallow trench isolation (STI) substrate. A selective coverage is provided to protect the height of the Si-STI substrate and an Si-STI interface. A desirable geometry can be obtained for forming a silicon germanium (SiGe)layer with uniform thickness near the divot.
    Type: Application
    Filed: April 20, 2015
    Publication date: July 28, 2016
    Inventors: Quanbo Li, Jun Huang, Xiangguo Meng
  • Patent number: 9390915
    Abstract: A process is used to form a protective layer to cover a divot between two regions of a semiconductor material. During etching processes, the protective layer protects the divot to be etched away and reduces material loss of a Silicon (Si)-shallow trench isolation (STI) substrate. A selective coverage is provided to protect the height of the Si-STI substrate and an Si-STI interface. A desirable geometry can be obtained for forming a silicon germanium (SiGe)layer with uniform thickness near the divot.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: July 12, 2016
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Quanbo Li, Jun Huang, Xiangguo Meng
  • Publication number: 20150270127
    Abstract: The invention discloses a treatment process for a semiconductor, comprising providing a substrate, the substrate comprises silicon material; defining a trench region; removing the trench region using a plasma etching process and exposing a trench surface, the trench surface comprising surface defects; forming an oxidation layer overlaying the trench surface; removing the oxidation layer and at least a portion of the surface defects; expositing a treated trench surface, the treated trench surface being substantially free from surface defects; and forming a layer of silicon germanium material overlaying the treated trench surface. The invention further provides a semiconductor processing technique used to eliminate or reduce dislocation defect on the semiconductor device and improve device performance. In the treatment process, a substrate is subjected to at least one oxidation-deoxidation processes, where an oxidation layer is formed and then removed.
    Type: Application
    Filed: January 6, 2015
    Publication date: September 24, 2015
    Inventors: Quanbo Li, Jun Huang, Xiangguo Meng, Yu Zhang
  • Car
    Patent number: D920161
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 25, 2021
    Assignee: SUZHOU GOLDEN RIDGE INTELLIGENCE SCIENCE & TECHNOLOGY CO., LTD.
    Inventors: Jiaxin Li, Weirong Liu, Yin Jiao, Xiangguo Meng, Li Yan