Abstract: The invention relates to an apparatus for virtualized registers. The apparatus includes register space, group selectors, and a block selector. The register space is divided into physical blocks, each of which includes register groups, and each register group contains registers. Each group selector is coupled to a portion of the register groups in a corresponding physical block, and is arranged operably to enable one of the portion of the register groups in the corresponding physical block in accordance with a first control signal corresponding to a virtual device, or a function performed by the virtual device. The block selector, coupled to the group selectors, is arranged operably to enable one of the group selectors in accordance with a second control signal corresponding to a virtual machine instruction. The virtual machine instruction is translated into an operation of the virtual device.

Abstract: An artificial intelligence chip and a data operation method are provided. The artificial intelligence chip receives a command carrying first data and address information and includes a chip memory, a computing processor, a base address register, and an extended address processor. The base address register is configured to access an extended address space in the chip memory. The extended address processor receives the command. The extended address processor determines an operation mode of the first data according to the address information. When the address information points to a first section of the extended address space, the extended address processor performs a first operation on the first data. When the address information points to a section other than the first section of the extended address space, the extended address processor notifies the computing processor of the operation mode and the computing processor performs a second operation on the first data.

Abstract: An artificial intelligence chip and a data operation method are provided. The artificial intelligence chip receives a command carrying first data and address information and includes a chip memory, a computing processor, a base address register, and an extended address processor. The base address register is configured to access an extended address space in the chip memory. The extended address processor receives the command. The extended address processor determines an operation mode of the first data according to the address information. When the address information points to a first section of the extended address space, the extended address processor performs a first operation on the first data. When the address information points to a section other than the first section of the extended address space, the extended address processor notifies the computing processor of the operation mode and the computing processor performs a second operation on the first data.

Abstract: The invention relates to an apparatus for virtualized registers. The apparatus includes register space, group selectors, and a block selector. The register space is divided into physical blocks, each of which includes register groups, and each register group contains registers. Each group selector is coupled to a portion of the register groups in a corresponding physical block, and is arranged operably to enable one of the portion of the register groups in the corresponding physical block in accordance with a first control signal corresponding to a virtual device, or a function performed by the virtual device. The block selector, coupled to the group selectors, is arranged operably to enable one of the group selectors in accordance with a second control signal corresponding to a virtual machine instruction. The virtual machine instruction is translated into an operation of the virtual device.