Abstract: Disclosed are a zinc-based metal organic nanoparticle and a preparation method therefor, and a photoresist. The zinc-based metal organic nanoparticle has a core-shell structure, and the general formula is ZnxOy[A]2x[B]2, wherein x is 2 or 3, and 2x?y?4x, ZnxOy is a kernel of the core-shell structure, A is a first organic ligand, B is a second organic ligand, the first organic ligand A and the second organic ligand B together form an outer shell of the core-shell structure, the first organic ligand A is selected from one or more of a substituted or unsubstituted aliphatic group and a substituted or unsubstituted aromatic group, and the second organic ligand B is selected from one or more of an organic amine and a derivative thereof.

Abstract: There is a method for making a high-performance opto-electronic device on an amorphous substrate. The method includes growing on a single-crystal substrate, a single-crystal, oxide film; applying a first chemical processing to the single-crystal, oxide film to obtain a first transferrable, single-crystal, chalcogenide film; transferring the transferrable, single crystal, chalcogenide film from the single-crystal substrate to an amorphous substrate or polycrystalline metal substrate; applying a second chemical processing to the transferrable, single-crystal, chalcogenide film to obtain a single-crystal, non-oxide film, wherein the single-crystal, non-oxide film is different from the transferrable, single-crystal, chalcogenide film; and growing a wide-bandgap semiconductor film using the single-crystal, non-oxide film as a seeding layer to obtain the opto-electronic device on the amorphous glass or polycrystalline metal substrate. The first chemical processing is different from the second chemical processing.

Abstract: There is a method for forming an oxide or chalcogenide 2D semiconductor. The method includes a step of growing on a substrate, by a deposition method, a precursor epitaxy oxide or chalcogenide film; and a step of sulfurizing the precursor epitaxy oxide or chalcogenide film, by replacing the oxygen atoms with sulfur atoms, to obtain the oxide or chalcogenide 2D semiconductor. The oxide or chalcogenide 2D semiconductor has an epitaxy structure inherent from the precursor epitaxy oxide or chalcogenide film.

Abstract: A capacitor includes a first terminal, a second terminal, a first capacitor, and a second capacitor. The first capacitor includes at least two first conductors arranged in a first direction, where each two adjacent first conductors in the at least two first conductors are separated by a first dielectric, a part of the at least two first conductors is electrically coupled to the first terminal, and the other part of the at least two first conductors is electrically coupled to the second terminal. The second capacitor includes at least two second conductors arranged in a second direction, where each two adjacent second conductors in the at least two second conductors are separated by a second dielectric, a part of the at least two second conductors is electrically coupled to the first terminal, and the other part of the at least two second conductors is electrically coupled to the second terminal.

Abstract: A stacked inductor with different metal thickness and metal width. The stacked inductor comprises top and bottom metal traces which are aligned with each other. The thickness and width of the top and bottom metal traces are different. The top and bottom metal traces are connected at the end of metal trace with via holes. The inductance is increased with the use of the mutual inductance between top and bottom metal layers The parasitic resistor is reduced due to the difference of the top and bottom metal widths.

Abstract: A stacked inductor with combined metal layers is represented in this invention. The stacked inductor includes: a top layer metal coil, and at least two lower layer metal coils, the metal coils being aligned with each other; adjacent metal coils being connected at the corresponding ends through a via; wherein, each of the lower layer metal coils is consisted of plural layers of metal lines which are interconnected. With the same chip area, the stacked inductor of the present invention can achieve higher inductance and Q factor because of the mutual inductance generated from the plural layers of metal lines and the reduced parasitic resistance.

Abstract: A structure of stack differential inductor is represented in this invention; this structure includes top and bottom metal traces, which are aligned with each other and symmetric. Starting from one port and after half turn, the top metal trace is connected to bottom metal trace through via holes. Meanwhile, after another half turn, the bottom trace is connected to top trace through via holes. The inductance is increased by means of this method. With the same chip area, this stack differential inductor possesses larger inductance and higher Q factor because of the larger mutual inductance between top and bottom metal than conventional differential inductor.

Abstract: A stacked inductor with different metal thickness and metal width is represented in this invention, this structure comprise: top and bottom metal trace, which is aligned with each other. The thickness and width of top and bottom metal trace are different. The top and bottom metal trace are connected at the end of metal trace with via holes. The inductance is increased with the use of the mutual inductance between top and bottom metal layers, and the parasitic resistor is reduced by means of different top and bottom metal width. This stacked inductor possesses larger inductance than single layer spiral inductor with relatively higher Q factor.

Abstract: A multi-path stacked inductor for current compensation is represented in this invention. This structure includes top and bottom metal trace, which are aligned with each other. Each metal trace consists of multi paths. The inner path in top metal flips over to the outer path in the bottom metal, while the outer path in top metal flips over to the inner path in the bottom metal. These paths join together at the end of the metal trace with via holes. Skin effect and current crowding effect are reduced by means of this method. This stacked inductor possesses larger inductance than single layer spiral inductor, with relatively higher Q factor.

Abstract: A manufacture method for IC process with top and top-1 metal layers thickened and stacked inductor manufactured by this method is represented in this invention. This method includes: with multi metal layers, and the thickness of top and top-1 metal layers are more than 2.8 um. Thickened top and top-1 metal layers can reduce the resistance of top and top-1 metal layers, so can increase the Q factor of inductor.

Abstract: A stacked inductor with combined metal layers is represented in this invention. The stacked inductor includes: a top layer metal coil, and at least two lower layer metal coils, the metal coils being aligned with each other; adjacent metal coils being connected at the corresponding ends through a via; wherein, each of the lower layer metal coils is consisted of plural layers of metal lines which are interconnected. With the same chip area, the stacked inductor of the present invention can achieve higher inductance and Q factor because of the mutual inductance generated from the plural layers of metal lines and the reduced parasitic resistance.

Abstract: A Multi-Oxide OTP (one time programmable) device is provided having different thicknesses of the gate oxide region at the transistor side and at the capacitor side, respectively, to increase the coupling efficiency of the capacitive transistor therein and improve the OTP programming rate. The present invention can be applicable to semiconductor integrated circuits and discrete components. More particularly, to single-poly EEPROM device.