Patents by Inventor Xiangqun Sun

Xiangqun Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fractional-N baseband frequency synthesizer in bluetooth applications
    Patent number: 7471123
    Abstract: A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: December 30, 2008
    Assignee: Agere Systems Inc.
    Inventors: William Eric Holland, Wenzhe Luo, Zhigang Ma, Dale H. Nelson, Harold Thomas Simmonds, Lizhong Sun, Xiangqun Sun
  • Fractional-N baseband frequency synthesizer in bluetooth applications
    Publication number: 20060238226
    Abstract: A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).
    Type: Application
    Filed: April 20, 2005
    Publication date: October 26, 2006
    Inventors: William Holland, Wenzhe Luo, Zhigang Ma, Dale Nelson, Harold Simmonds, Lizhong Sun, Xiangqun Sun
  • Fractional-N baseband frequency synthesizer in bluetooth applications
    Patent number: 6946884
    Abstract: A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: September 20, 2005
    Assignee: Agere Systems Inc.
    Inventors: William Eric Holland, Wenzhe Luo, Zhigang Ma, Dale H. Nelson, Harold Thomas Simmonds, Lizhong Sun, Xiangqun Sun
  • Fractional-N baseband frequency synthesizer in bluetooth applications
    Publication number: 20030201805
    Abstract: A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).
    Type: Application
    Filed: April 25, 2002
    Publication date: October 30, 2003
    Inventors: William Eric Holland, Wenzhe Luo, Zhigang Ma, Dale H. Nelson, Harold Thomas Simmonds, Lizhong Sun, Xiangqun Sun