Abstract: A laterally diffused metal oxide semiconductor structure can include: a base layer; a source region and a drain region located in the base layer; first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; and a second conductor at least partially located on the voltage withstanding layer, where the first and second conductors are spatially isolated, and a juncture region of the first dielectric layer and the voltage withstanding layer is covered by one of the first and second conductors.

Abstract: A laterally diffused metal oxide semiconductor device can include: a base layer; a source region and a drain region located in the base layer; a first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; a second conductor at least partially located on the voltage withstanding layer; and a source electrode electrically connected to the source region, where the first and second conductors are spatially isolated, and the source electrode at least covers a space between the first and second conductors.

Abstract: A method of manufacturing an optoelectronic integrated device can include: providing a semiconductor substrate including at least one optoelectronic device in the semiconductor substrate; forming a first dielectric layer on a first surface of the semiconductor substrate; forming a multilayer insulating layer on the first dielectric layer; forming a first opening in the multilayer insulating layer to expose the first dielectric layer above the optoelectronic device area; and forming a second dielectric layer on the dielectric layer, where the first dielectric layer and the second dielectric layer are anti-reflection layers.

Abstract: Disclosed is a field effect transistor (FET) and a method for manufacturing the same, the FET comprises: a substrate, a first well region located on the substrate, a second well region, a body contact region, a source region, a drain region and a gate conductor. The body contact region, the source region and the drain region are located in the first well region, the doping concentration of the second well region is higher than that of the first well region. A parasitic bipolar junction transistor (BJT) is located in the field effect transistor, current flowing through the BJT is controlled by adjusting doping concentration or area of the second well region. The second well region is formed in the first well region, so that the holding voltage of the FET is improved, and finally effect on the FET caused by the current flowing through the BJT can be weakened.

Abstract: A laterally diffused metal oxide semiconductor device can include: a base layer; a source region and a drain region located in the base layer; a first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; a second conductor at least partially located on the voltage withstanding layer; and a source electrode electrically connected to the source region, where the first and second conductors are spatially isolated, and the source electrode at least covers a space between the first and second conductors.

Abstract: A method of manufacturing an optoelectronic integrated device can include: providing a semiconductor substrate including at least one optoelectronic device in the semiconductor substrate; forming a first dielectric layer on a first surface of the semiconductor substrate; forming a multilayer insulating layer on the first dielectric layer; forming a first opening in the multilayer insulating layer to expose the first dielectric layer above the optoelectronic device area; and forming a second dielectric layer on the dielectric layer, where the first dielectric layer and the second dielectric layer are anti-reflection layers.

Abstract: A laterally diffused metal oxide semiconductor device can include: a base layer; a source region and a drain region located in the base layer; a first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; a second conductor at least partially located on the voltage withstanding layer; and a source electrode electrically connected to the source region, where the first and second conductors are spatially isolated, and the source electrode at least covers a space between the first and second conductors.

Abstract: A laterally diffused metal oxide semiconductor structure can include: a base layer; a source region and a drain region located in the base layer; first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; and a second conductor at least partially located on the voltage withstanding layer, where the first and second conductors are spatially isolated, and a juncture region of the first dielectric layer and the voltage withstanding layer is covered by one of the first and second conductors.

Abstract: A laterally diffused metal oxide semiconductor structure can include: a base layer; a source region and a drain region located in the base layer; first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; and a second conductor at least partially located on the voltage withstanding layer, where the first and second conductors are spatially isolated, and a juncture region of the first dielectric layer and the voltage withstanding layer is covered by one of the first and second conductors.

Abstract: A laterally diffused metal oxide semiconductor device can include: a base layer; a source region and a drain region located in the base layer; a first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; a second conductor at least partially located on the voltage withstanding layer; and a source electrode electrically connected to the source region, where the first and second conductors are spatially isolated, and the source electrode at least covers a space between the first and second conductors.

Abstract: A laterally diffused metal oxide semiconductor structure can include: a base layer; a source region and a drain region located in the base layer; first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; and a second conductor at least partially located on the voltage withstanding layer, where the first and second conductors are spatially isolated, and a juncture region of the first dielectric layer and the voltage withstanding layer is covered by one of the first and second conductors.

Abstract: The present application relates to a remote exposure control device, a digital radiography system and an exposing method for the system. The remote exposure control device comprises: a power source module, a sensing module electrically connected to the power source module, a processing module electrically connected to the power source module, and a communication module, wherein: the sensing module is electrically connected to the communication module and the processing module respectively; the communication module is configured to communicate with a flat panel detector (FPD) paired with a digital radiography system; and the processing module is configured to, after receiving a trigger signal sent by the sensing module, control the communication module to send an awakening instruction or a power-on instruction to the FPD, so that the FPD is awakened from a sleeping state or a power-off state to a working state.

Abstract: The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the semiconductor substrate in a second region. A dopant of a first type is implanted with the first gate stack and the second gate stack as a hard mask to form a lightly-doped drain region of the first type. A dopant of a second type is implanted by using a first mask and with the second gate stack as a hard mask to form a lightly-doped drain region of the second type. The first mask blocks the first region and exposes the second region. When the lightly-doped drain region of the second type is formed, the dopant of the second type over dopes a predetermined region of the lightly-doped drain region of the first type.

Abstract: Disclosed is a field effect transistor (FET) and a method for manufacturing the same, the FET comprises: a substrate, a first well region located on the substrate, a second well region, a body contact region, a source region, a drain region and a gate conductor. The body contact region, the source region and the drain region are located in the first well region, the doping concentration of the second well region is higher than that of the first well region. A parasitic bipolar junction transistor (BJT) is located in the field effect transistor, current flowing through the BJT is controlled by adjusting doping concentration or area of the second well region. The second well region is formed in the first well region, so that the holding voltage of the FET is improved, and finally effect on the FET caused by the current flowing through the BJT can be weakened.

Abstract: The present disclosure relates to a method for manufacturing a CM OS structure. Shallow trench isolation is formed in a semiconductor substrate. A first region is defined for a first MOSFET and a second MOSFET of a first type and a second region is defined for a third MOSFET and a fourth MOSFET of a second type, by shallow trench isolation. First to fourth Gates sacks are formed on the semiconductor substrate, each of which includes a gate conductor and a gate dielectric and the gate dielectric is disposed between the gate conductor and the semiconductor substrate. The first and second gate stacks are formed in the first region, and the third and fourth gate stacks are formed in the second region. The gate dielectrics of the first and third gate stacks have a first thickness, and the gate dielectrics of the second and fourth gate stacks have a second thickness larger than the first thickness. Some masks are commonly used in various steps in this process so that the number of the masks is reduced.

Abstract: The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the semiconductor substrate in a second region. A dopant of a first type is implanted with the first gate stack and the second gate stack as a hard mask to form a lightly-doped drain region of the first type. A dopant of a second type is implanted by using a first mask and with the second gate stack as a hard mask to form a lightly-doped drain region of the second type. The first mask blocks the first region and exposes the second region. When the lightly-doped drain region of the second type is formed, the dopant of the second type over dopes a predetermined region of the lightly-doped drain region of the first type. In such a process, over doping is used for reducing the number of masks. A doping concentration of a well region may be modified to adjust work function.

Abstract: The present application relates to a remote exposure control device, a digital radiography system and an exposing method for the system. The remote exposure control device comprises: a power source module, a sensing module electrically connected to the power source module, a processing module electrically connected to the power source module, and a communication module, wherein: the sensing module is electrically connected to the communication module and the processing module respectively; the communication module is configured to communicate with a flat panel detector (FPD) paired with a digital radiography system; and the processing module is configured to, after receiving a trigger signal sent by the sensing module, control the communication module to send an awakening instruction or a power-on instruction to the FPD, so that the FPD is awakened from a sleeping state or a power-off state to a working state.

Abstract: The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the semiconductor substrate in a second region. A dopant of a first type is implanted with the first gate stack and the second gate stack as a hard mask to form a lightly-doped drain region of the first type. A dopant of a second type is implanted by using a first mask and with the second gate stack as a hard mask to form a lightly-doped drain region of the second type. The first mask blocks the first region and exposes the second region. When the lightly-doped drain region of the second type is formed, the dopant of the second type over dopes a predetermined region of the lightly-doped drain region of the first type. In such a process, over doping is used for reducing the number of masks. A doping concentration of a well region may be modified to adjust work function.

Abstract: The present disclosure relates to a method for manufacturing a CM OS structure. Shallow trench isolation is formed in a semiconductor substrate. A first region is defined for a first MOSFET and a second MOSFET of a first type and a second region is defined for a third MOSFET and a fourth MOSFET of a second type, by shallow trench isolation. First to fourth Gates sacks are formed on the semiconductor substrate, each of which includes a gate conductor and a gate dielectric and the gate dielectric is disposed between the gate conductor and the semiconductor substrate. The first and second gate stacks are formed in the first region, and the third and fourth gate stacks are formed in the second region. The gate dielectrics of the first and third gate stacks have a first thickness, and the gate dielectrics of the second and fourth gate stacks have a second thickness larger than the first thickness. Some masks are commonly used in various steps in this process so that the number of the masks is reduced.

Abstract: An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area.