Abstract: A battery cell includes a housing. The housing includes a first wall and a second wall, where the first wall and the second wall are welded to form a first welding zone, the first wall includes a first zone and a second zone arranged along a first direction, the first zone is arranged adjacent to the first welding zone, a thickness of the first zone is greater than a thickness of the second zone, and the first direction is parallel to a thickness direction of the second wall.

Abstract: A liquid crystal display panel is provided and includes an array substrate, which includes a display region and a non-display region. The non-display region is provided with a gate driver on array (GOA) signal line and a frame sealant located above the GOA signal line. A spacer layer includes a first spacer disposed near an edge of the display region, a second spacer disposed and distributed in the display region, and a third spacer disposed in the non-display region, located between the GOA signal line and the frame sealant.

Abstract: The present disclosure provides a liquid crystal display panel and a device, which comprises a data line, a scanning line, a first common line, a second common line, a main-pixel portion, and a sub-pixel portion. The first common line is for supplying a common voltage, the second common is for making a voltage of the sub-pixel portion equal to a fixed value and a voltage of the main-pixel portion is different from the voltage of the sub-pixel portion when the liquid crystal display panel is aligned.

Abstract: A 3T pixel structure is provided. The 3T pixel structure includes: a substrate, on which a lower common electrode and a scan line are positioned; a first dielectric layer, positioned on the lower common electrode, the scan line and the substrate; a charge-sharing thin film transistor (TFT), including a source, a drain, and a gate, the source and the drain of the charge-sharing TFT being positioned on the first dielectric layer; a data line, positioned on the first dielectric layer; a second dielectric layer, positioned on the source, the drain, the data line of the charge-sharing TFT and the first dielectric layer; and an upper common electrode, positioned on the second dielectric layer. The second dielectric layer has a source hole to allow the upper common electric layer to contact the first source and electrically connect to the first source through the source hole.

Abstract: The present disclosure provides a liquid crystal display panel and a device, which comprises a data line, a scanning line, a first common line, a second common line, a main-pixel portion, and a sub-pixel portion. The first common line is for supplying a common voltage, the second common is for making a voltage of the sub-pixel portion equal to a fixed value and a voltage of the main-pixel portion is different from the voltage of the sub-pixel portion when the liquid crystal display panel is aligned.

Abstract: A 3T pixel structure is provided. The 3T pixel structure includes: a substrate, on which a lower common electrode and a scan line are positioned; a first dielectric layer, positioned on the lower common electrode, the scan line and the substrate; a charge-sharing thin film transistor (TFT), including a source, a drain, and a gate, the source and the drain of the charge-sharing TFT being positioned on the first dielectric layer; a data line, positioned on the first dielectric layer; a second dielectric layer, positioned on the source, the drain, the data line of the charge-sharing TFT and the first dielectric layer; and an upper common electrode, positioned on the second dielectric layer. The second dielectric layer has a source hole to allow the upper common electric layer to contact the first source and electrically connect to the first source through the source hole.

Abstract: An array substrate includes a transparent substrate, at least one gate line, at least one data line, and at least one storage electrode line arranged on the transparent substrate, and at least one switch component arranged at an intersection of the gate line and the data line. The gate line and the data line are insulated from each other to define a pixel area, and the storage electrode line is arranged within the pixel area. The control end and the input end of the switch component respectively connect to the gate line and the data line, and the output end of the switch component extends into the pixel area so as to be opposite to the storage electrode line, and the output end and the storage electrode line are insulated from each other.