Abstract: A clock spread spectrum circuit, an electronic equipment, and a clock spread spectrum method are disclosed. The clock spread spectrum circuit includes a control circuit, a signal generation circuit, and a duty cycle adjustment circuit. The duty cycle adjustment circuit is configured to generate a target voltage having a duty cycle that is equal to a target duty cycle, the control circuit is configured to generate a frequency control word according to a modulation parameter, and the frequency control word changes discretely with time; and the signal generation circuit is configured to receive the target voltage and the frequency control word and generate and output a spread spectrum output signal that is spectrum-spread according to the target voltage and the frequency control word, and the spread spectrum output signal corresponds to the frequency control word and a duty cycle of the spread spectrum output signal is the target duty cycle.

Abstract: A pulse width modulation (PWM) circuit, a method for PWM, and an electronic device are provided. In the PWM circuit, a control word providing circuit can generate, based on an obtained target duty cycle, two target frequency control words with a ratio of the target duty cycle, and output the two target frequency control words to a pulse generation circuit, wherein a ratio of the first target frequency control word to the second target frequency control word is the target duty cycle; and the pulse generation circuit can output a target pulse signal with the target duty cycle under the control of the two target frequency control words.

Abstract: An optical communication device, an optical communication system, and a method for establishing a communication connection are provided, relating to communications technology. In the optical communication device, the first driving circuit can control, based on the generated first target plaintext, the optical signal transmitting circuit to transmit the first optical signal, and control, based on the generated first key, the optical signal transmitting circuit to transmit the second optical signal. That is, an optical communication device that detects the optical signals can establish, based on the optical signals, a communication connection with the optical communication device that transmits the optical signals.

Abstract: Provide is a FIFO memory system. The FIFO memory system includes: a FIFO memory; a read clock frequency circuit, configured to provide at least two clock signals, wherein the at least two clock signals include a first clock signal and a second clock signal, a frequency of the first clock signal being greater than a frequency of the second clock signal; and a controller, configured to determine a data volume in the FIFO memory, control the read clock frequency circuit to output the first clock signal in a case that the data volume in the FIFO memory is in a first range, or control the read clock frequency circuit to output the second clock signal in a case that the data volume in the FIFO memory is in a second range, the lower limit of the first range being not less than an upper limit of the second range.

Abstract: A clock spread spectrum circuit, an electronic equipment, and a clock spread spectrum method are disclosed. The clock spread spectrum circuit (10) includes a control circuit (11) and a signal generation circuit (12). The control circuit (11) is configured to generate a frequency control word according to a modulation parameter, and the frequency control word changes discretely with time; and the signal generation circuit (12) is configured to receive the frequency control word and generate and output a spread spectrum output signal that is spectrum-spread according to the frequency control word, and the spread spectrum output signal corresponds to the frequency control word.

Abstract: The present disclosure provides a hash algorithm circuit, a hash algorithm method, and an electronic device. The hash algorithm circuit is used to reduce fixed-length parallel data, and the reduced identifier can be used as an index reference, an identifier ID, an address extension bit, information summary, and so on. The hash algorithm circuit has the characteristics of low power consumption, low cost, etc., and can be integrated in a digital circuit.

Abstract: An integrated circuit is provided. The integrated circuit includes: a clock source configured to: generate a clock signal of the integrated circuit; at least two functional circuits; and at least two clock generators corresponding to the functional circuits and configured to: determine initial phases of the corresponding functional circuits, and generate clock signals of the functional circuits based on the clock signal of the integrated circuit and the initial phases, so as to keep the clock signals of all the functional circuits synchronized, wherein the initial phases are determined based on transmission distances, over which the clock signal of the integrated circuit is transmitted from the clock source to the functional circuits, and loads of the functional circuits.

Abstract: Provided is an interactive authentication method, applicable to a transmitter. The transmitter is communicatively connected to a receiver. The authentication method includes: generating a first challenge and transmitting the first challenge to the receiver; receiving a response from the receiver, wherein the response comprises first identity authentication information and a second challenge, the first identity authentication information and the second challenge being encrypted using a first identity authentication key; generating, based on the first challenge, a second identity authentication key and second identity authentication information; and decrypting the first identity authentication information using the second identity authentication key, and performing identity authentication by matching the decrypted first identity authentication information with the second identity authentication information.

Abstract: A digital fingerprint generation circuit based on an integrated circuit is provided. In the digital fingerprint generation circuit, a control unit is configured to: generate a first control word and a second control word, and transmit the first control word and the second control word to a first clock generator and a second clock generator respectively, so that the first clock generator generates a first clock signal based on the first control word, and the second clock generator generates a second clock signal based on the second control word; and a frequency detector generates a digital fingerprint of the integrated circuit based on the first clock signal and the second clock signal.

Abstract: An integrated circuit is provided. The integrated circuit includes: a clock source configured to: generate a clock signal of the integrated circuit; at least two functional circuits; and at least two clock generators corresponding to the functional circuits and configured to: determine initial phases of the corresponding functional circuits, and generate clock signals of the functional circuits based on the clock signal of the integrated circuit and the initial phases, so as to keep the clock signals of all the functional circuits synchronized, wherein the initial phases are determined based on transmission distances, over which the clock signal of the integrated circuit is transmitted from the clock source to the functional circuits, and loads of the functional circuits.

Abstract: Provided is a digital fingerprint generator. The digital fingerprint generator includes: a control circuit, configured to generate a control word; a first pulse generation circuit, connected to the control circuit, and configured to output a first pulse signal in response to the control word; a second pulse generation circuit, connected to the control circuit, having a same structure as the first pulse generation circuit, and configured to output a second pulse signal in response to the control word; and an output circuit, connected to the first pulse generation circuit and the second pulse generation circuit, and configured to output a digital fingerprint based on the first pulse signal and the second pulse signal according to a predetermined first rule.

Abstract: A method for generating spread-spectrum synchronous clock signals includes comparing an input signal of a first frequency with a feedback signal of a second frequency in a loop of feedback; generating a first control signal and a second control signal; determining an integer part I of a control word F to track the first frequency; registering n levels for the first control signal and the second control signal to introduce n phase delays for randomly changing a fraction part r (0<r<1) of the control word F to provide a broadened boundary in frequency spectrum; and generating a synthesized periodic signal with the second frequency based on a base time unit ?, the first frequency, and the control word F, the synthesized periodic signal being fed back as the feedback signal in the loop of feedback and outputted with the second frequency being locked within the broadened boundary.

Abstract: The present application discloses a circuit for generating spread-spectrum synchronous clock signal. The circuit includes a frequency detector comprising a fraction controller configured to compare an input signal of a first frequency with a feedback signal of a second frequency in a loop of feedback to generate a first control signal and a second control signal alternately for determining a control word to track the first frequency and a phase-shift controller configured to register n levels for the first control signal and the second control signal to introduce n phase delays for changing a fraction part of the control word randomly to provide a broadened boundary. The circuit also includes a digitally controlled oscillator configured to generate a synthesized periodic signal based on a base time unit, the first frequency, and the control word, with the second frequency being locked within the broadened boundary of the first frequency.

Abstract: A data processing method, including: obtaining a challenge sequence of challenge-response pairs, and generating, by a physical unclonable function, an original response sequence corresponding to the challenge-response pairs; generating a first index parameter according to the challenge sequence, and obtaining feature bit information in the original response sequence according to the first index parameter; converting the challenge sequence to generate a second index parameter, and updating the first index parameter according to the second index parameter and the feature bit information; obtaining new feature bit information in the original response sequence according to the updated first index parameter; and repeatedly generating second index parameters, updating the first index parameter according to the second index parameters and the latest obtained feature bit information, and obtaining multiple pieces of feature bit information, to generate a target response sequence according to the multiple pieces of fe

Abstract: Provided is a security protection method for a heterogeneous system, wherein the heterogeneous system includes a processor. The processor includes a first region, wherein the first region includes a physical unclonable function circuit. The method includes: detecting whether an input of the heterogeneous system is abnormal; acquiring a configuration file in response to the input of the heterogeneous system being detected as abnormal, wherein the acquired configuration file is different from a configuration file of the physical unclonable function circuit that has run; and reconstructing, on the processor, a mapping of the physical unclonable function circuit based on the acquired configuration file.

Abstract: Provided is a clock signal generation circuit. The clock signal generation circuit includes a control word generation circuit, an initial clock generation circuit and a spread spectrum clock generation circuit, wherein the control word generation circuit is connected to the initial clock generation circuit and the spread spectrum clock generation circuit; the initial clock generation circuit is further connected to the spread spectrum clock generation circuit.

Abstract: This is provided a time synchronization method, including: an adjustment stage including N adjustment cycles, N being an integer greater than 1; in each adjustment cycle, generating a physical clock signal at least according to a pre-acquired frequency control word corresponding to the adjustment cycle, and obtaining logical time at least according to the physical clock signal and a physical time deviation; a clock slope of the physical clock signal generated in each adjustment cycle reaches its corresponding target value, and the target values of the clock slopes of the physical clock signals in the N adjustment cycles gradually approach 1; the physical time deviation is: a time difference between the reference time and the physical time corresponding to the physical clock signal in an Nth adjustment cycle at the end of the Nth adjustment cycle. A time synchronization device and a network node device are provided.

Abstract: A data processing circuit, a data processing method, and an electronic device are provided. The data processing circuit includes a first data processing sub-circuit and a second data processing sub-circuit. An output terminal of the first data processing sub-circuit is connected to an input terminal of the second data processing sub-circuit. The first data processing sub-circuit is configured to receive an original sequence to generate a first processed sequence. Each of first processed numbers in the first processed sequence is calculated from at least two pieces of original data in the original data. The second data processing sub-circuit is configured to receive the first processed sequence to generate a second processed sequence.

Abstract: Embodiments of the present disclosure provide a circuit and a method for digital fingerprint generation, and an electronic device. The digital fingerprint generation method includes inputting an input signal from outside; generating a frequency relationship indication signal between an input signal and a feedback signal; generating a frequency control signal based on the frequency relationship indication signal; generating an intermediate signal based on a frequency control signal and pulse signals; dividing the intermediate signal in frequency to generate the feedback signal; and generating a digital fingerprint based on the input signal and the feedback signal.

Abstract: A clock signal generation circuit, a method for generating a clock signal, and an electronic device are provided, relating to the field of communications technology. In the clock signal generation circuit, an initial clock providing circuit can generate an initial clock signal having an initial frequency; a control word providing circuit can determine a target frequency offset of the initial frequency based on a detected target parameter and generate a frequency control word based on the target frequency offset; a target clock generating circuit can generate a target clock signal having a target output frequency based on the frequency control word and the initial clock signal, wherein the target output frequency is negatively correlated with a value of the frequency control word and positively correlated with the initial frequency.