Abstract: A power-on reset circuit is provided. During a power-on process of the power-on reset circuit, a threshold voltage of an output signal rstn jumping from a low level to a high level is adjusted by clamp of a voltage at a node c and voltage division between a first resistor and a second resistor, and is controlled to be greater than a threshold voltage of a metal oxide semiconductor device. During a power-off process of the power-on reset circuit, a threshold voltage of the output signal rstn jumping from the high level to the low level is adjusted by increasing a voltage at a node d by means of a third resistor and voltage division between the first resistor and the third resistor, and is controlled to be greater than the threshold voltage of the metal oxide semiconductor device.

Abstract: A Biphase Mark Coding (BMC) transceiver is provided. In the BMC transceiver, an operational amplifier operating in a time division multiplexing manner is used. The operational amplifier is configured as a unity gain buffer, and it is determined whether the BMC transceiver operates as a transmitter or a receiver by selecting different input switches and output switches. In a transmitting mode, a bias current of an input differential pair transistor of the operational amplifier is changed, to change a slew rate, so as to obtain an output waveform with adjustable rising/falling edges of the transmitter.

Abstract: A biphase mark coding transmitter is provided. In the biphase mark coding transmitter, a delay control unit performs equal-interval delay processing on data transmitted by a data coding and protocol processing unit. Then, the current-steering digital-to-analog converter is controlled to charge or discharge a resistance-capacitance circuit to obtain an accurately-controlled conversion time. Data with the controlled conversion time is driven to a CC by a unity-gain buffer to generate an output waveform. The technical solution solves the technical problem of a mutual influence between power source systems of a traditional BMC transmitter which is a digital module and a traditional BMC receiver which is an analog module, and the technical problem of a large noise of a power switch and large consumption of chip area and power which are resulted from digital buffers driven by equal-interval data or clocks in a traditional BMC transmitter.

Abstract: A display device and a method for manufacturing the display device are provided.

Abstract: An input signal decoding circuit for a receiver side in a mobile industry processor interface (MIPI) C-Phy is provided, which includes: an equalizer circuit module connected to a transmitter side of an MIPI via three signal wires and configured to sample signals of the signal wires to acquire a first data signal, a second data signal and a third data signal; a clock recovery circuit module configured to acquire an operating clock signal from the three data signals; a decoding circuit module configured to outputs a Flip signal, a Rotation signal and a Polarity signal based on the three data signals and the operating clock signal; and a serial-to-parallel conversion module configured to output 21-bit parallel data based on the Flip signal, the Rotation signal and the Polarity signal.

Abstract: An input signal decoding circuit for a receiver side in a mobile industry processor interface (MIPI) C-Phy is provided, which includes: an equalizer circuit module connected to a transmitter side of an MIPI via three signal wires and configured to sample signals of the signal wires to acquire a first data signal, a second data signal and a third data signal; a clock recovery circuit module configured to acquire an operating clock signal from the three data signals; a decoding circuit module configured to outputs a Flip signal, a Rotation signal and a Polarity signal based on the three data signals and the operating clock signal; and a serial-to-parallel conversion module configured to output 21-bit parallel data based on the Flip signal, the Rotation signal and the Polarity signal.

Abstract: The termination resistor calibration circuit and a control method thereof are provided. The resistance of the termination resistor of the CML transmitter is directly calibrated, so that the error caused by duplicating the resistor can be avoided, which improves the calibration accuracy. In addition, no duplicated resistor and constant current source is required, which reduces the area occupied by the circuit. Further, the absolute current and the relative current are obtained from the bandgap module and thus have high accuracy. The output signal control module, the constant current source, and the termination resistors of the CML transmitter can be used for transmitting signals after the resistance calibration is finished, which improves the utilization of the circuit module.

Abstract: In an example, a server architecture is described for a dynamic cascaded node chain providing a resource cluster. The cascaded node chain may include one or more resource instances provisioned as a head node, zero or more middle nodes, and a tail node. Each node may include a discrete number of available resource entries in a flow table. As traffic enters the head node, each node attempts to match the traffic to an entry in its flow table. If no match is found, the packet is downlinked to the next node in the chain. If the packet reaches the tail node without a match, it is punted to the controller. The controller may then provision a matching entry if an entry is available. If not, the controller may spawn a new resource instance. When the full capacity of the cluster is reached, non-matching entries may be dropped.